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https://github.com/brain-hackers/u-boot-brain
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1d3d0f1f1c
This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection. Signed-off-by: Wills Wang <wills.wang@live.com>
72 lines
1.6 KiB
C
72 lines
1.6 KiB
C
/*
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* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <mach/ath79.h>
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#include <mach/ar71xx_regs.h>
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void _machine_restart(void)
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{
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void __iomem *base;
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u32 reg = 0;
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base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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if (soc_is_ar71xx())
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reg = AR71XX_RESET_REG_RESET_MODULE;
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else if (soc_is_ar724x())
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reg = AR724X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar913x())
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reg = AR913X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar933x())
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca953x())
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reg = QCA953X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca956x())
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reg = QCA956X_RESET_REG_RESET_MODULE;
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else
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puts("Reset register not defined for this SOC\n");
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if (reg)
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setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP);
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while (1)
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/* NOP */;
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}
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u32 get_bootstrap(void)
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{
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const void __iomem *base;
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u32 reg = 0;
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base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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if (soc_is_ar933x())
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reg = AR933X_RESET_REG_BOOTSTRAP;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_BOOTSTRAP;
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else if (soc_is_qca953x())
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reg = QCA953X_RESET_REG_BOOTSTRAP;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_BOOTSTRAP;
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else if (soc_is_qca956x())
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reg = QCA956X_RESET_REG_BOOTSTRAP;
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else
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puts("Bootstrap register not defined for this SOC\n");
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if (reg)
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return readl(base + reg);
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return 0;
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}
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