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mips: add base support for QCA/Atheros ath79 SOCs

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This patch add some common code for QCA/Atheros ath79 SOCs such as
DDR tuning, chip reset and CPU detection.

Signed-off-by: Wills Wang <wills.wang@live.com>
This commit is contained in:
Wills Wang 2016-03-16 16:59:52 +08:00 committed by Daniel Schwierzeck
parent 4a48cfc4e5
commit 1d3d0f1f1c
12 changed files with 1610 additions and 0 deletions
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6
arch/mips/Kconfig
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@ -55,6 +55,11 @@ config TARGET_PB1X00
select SYS_MIPS_CACHE_INIT_RAM_LOAD
select MIPS_TUNE_4KC
config ARCH_ATH79
bool "Support QCA/Atheros ath79"
select OF_CONTROL
select DM
config MACH_PIC32
bool "Support Microchip PIC32"
select OF_CONTROL
@ -67,6 +72,7 @@ source "board/imgtec/malta/Kconfig"
source "board/micronas/vct/Kconfig"
source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
source "arch/mips/mach-ath79/Kconfig"
source "arch/mips/mach-pic32/Kconfig"
if MIPS

1
arch/mips/Makefile
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@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/
libs-y += arch/mips/lib/
machine-$(CONFIG_SOC_AU1X00) += au1x00
machine-$(CONFIG_ARCH_ATH79) += ath79
machine-$(CONFIG_MACH_PIC32) += pic32
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))

6
arch/mips/include/asm/global_data.h
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@ -23,6 +23,12 @@ struct arch_global_data {
unsigned long tbl;
unsigned long lastinc;
#endif
#ifdef CONFIG_ARCH_ATH79
unsigned long id;
unsigned long soc;
unsigned long rev;
unsigned long ver;
#endif
};
#include <asm-generic/global_data.h>

7
arch/mips/mach-ath79/Kconfig Normal file
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@ -0,0 +1,7 @@
menu "QCA/Atheros 7xxx/9xxx platforms"
depends on ARCH_ATH79
config SYS_SOC
default "ath79"
endmenu

7
arch/mips/mach-ath79/Makefile Normal file
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@ -0,0 +1,7 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += reset.o
obj-y += cpu.o
obj-y += dram.o

142
arch/mips/mach-ath79/cpu.c Normal file
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@ -0,0 +1,142 @@
/*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ath79.h>
#include <mach/ar71xx_regs.h>
struct ath79_soc_desc {
enum ath79_soc_type soc;
const char *chip;
int major;
int minor;
};
static struct ath79_soc_desc desc[] = {
{ATH79_SOC_AR7130, "7130",
REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7130},
{ATH79_SOC_AR7141, "7141",
REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7141},
{ATH79_SOC_AR7161, "7161",
REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7161},
{ATH79_SOC_AR7240, "7240", REV_ID_MAJOR_AR7240, 0},
{ATH79_SOC_AR7241, "7241", REV_ID_MAJOR_AR7241, 0},
{ATH79_SOC_AR7242, "7242", REV_ID_MAJOR_AR7242, 0},
{ATH79_SOC_AR9130, "9130",
REV_ID_MAJOR_AR913X, AR913X_REV_ID_MINOR_AR9130},
{ATH79_SOC_AR9132, "9132",
REV_ID_MAJOR_AR913X, AR913X_REV_ID_MINOR_AR9132},
{ATH79_SOC_AR9330, "9330", REV_ID_MAJOR_AR9330, 0},
{ATH79_SOC_AR9331, "9331", REV_ID_MAJOR_AR9331, 0},
{ATH79_SOC_AR9341, "9341", REV_ID_MAJOR_AR9341, 0},
{ATH79_SOC_AR9342, "9342", REV_ID_MAJOR_AR9342, 0},
{ATH79_SOC_AR9344, "9344", REV_ID_MAJOR_AR9344, 0},
{ATH79_SOC_QCA9533, "9533", REV_ID_MAJOR_QCA9533, 0},
{ATH79_SOC_QCA9533, "9533",
REV_ID_MAJOR_QCA9533_V2, 0},
{ATH79_SOC_QCA9556, "9556", REV_ID_MAJOR_QCA9556, 0},
{ATH79_SOC_QCA9558, "9558", REV_ID_MAJOR_QCA9558, 0},
{ATH79_SOC_TP9343, "9343", REV_ID_MAJOR_TP9343, 0},
{ATH79_SOC_QCA9561, "9561", REV_ID_MAJOR_QCA9561, 0},
};
int arch_cpu_init(void)
{
void __iomem *base;
enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
u32 id, major, minor = 0;
u32 rev = 0, ver = 1;
int i;
base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
MAP_NOCACHE);
id = readl(base + AR71XX_RESET_REG_REV_ID);
major = id & REV_ID_MAJOR_MASK;
switch (major) {
case REV_ID_MAJOR_AR71XX:
case REV_ID_MAJOR_AR913X:
minor = id & AR71XX_REV_ID_MINOR_MASK;
rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
rev &= AR71XX_REV_ID_REVISION_MASK;
break;
case REV_ID_MAJOR_QCA9533_V2:
ver = 2;
/* drop through */
case REV_ID_MAJOR_AR9341:
case REV_ID_MAJOR_AR9342:
case REV_ID_MAJOR_AR9344:
case REV_ID_MAJOR_QCA9533:
case REV_ID_MAJOR_QCA9556:
case REV_ID_MAJOR_QCA9558:
case REV_ID_MAJOR_TP9343:
case REV_ID_MAJOR_QCA9561:
rev = id & AR71XX_REV_ID_REVISION2_MASK;
break;
default:
rev = id & AR71XX_REV_ID_REVISION_MASK;
break;
}
for (i = 0; i < ARRAY_SIZE(desc); i++) {
if ((desc[i].major == major) &&
(desc[i].minor == minor)) {
soc = desc[i].soc;
break;
}
}
gd->arch.id = id;
gd->arch.soc = soc;
gd->arch.rev = rev;
gd->arch.ver = ver;
return 0;
}
int print_cpuinfo(void)
{
enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
const char *chip = "????";
u32 id, rev, ver;
int i;
for (i = 0; i < ARRAY_SIZE(desc); i++) {
if (desc[i].soc == gd->arch.soc) {
chip = desc[i].chip;
soc = desc[i].soc;
break;
}
}
id = gd->arch.id;
rev = gd->arch.rev;
ver = gd->arch.ver;
switch (soc) {
case ATH79_SOC_QCA9533:
case ATH79_SOC_QCA9556:
case ATH79_SOC_QCA9558:
case ATH79_SOC_QCA9561:
printf("Qualcomm Atheros QCA%s ver %u rev %u\n", chip,
ver, rev);
break;
case ATH79_SOC_TP9343:
printf("Qualcomm Atheros TP%s rev %u\n", chip, rev);
break;
case ATH79_SOC_UNKNOWN:
printf("ATH79: unknown SoC, id:0x%08x", id);
break;
default:
printf("Atheros AR%s rev %u\n", chip, rev);
}
return 0;
}

16
arch/mips/mach-ath79/dram.c Normal file
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@ -0,0 +1,16 @@
/*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/sizes.h>
#include <asm/addrspace.h>
#include <mach/ddr.h>
phys_size_t initdram(int board_type)
{
ddr_tap_tuning();
return get_ram_size((void *)KSEG1, SZ_256M);
}

1184
arch/mips/mach-ath79/include/mach/ar71xx_regs.h Normal file
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File diff suppressed because it is too large Load Diff

143
arch/mips/mach-ath79/include/mach/ath79.h Normal file
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@ -0,0 +1,143 @@
/*
* Atheros AR71XX/AR724X/AR913X common definitions
*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_MACH_ATH79_H
#define __ASM_MACH_ATH79_H
#include <linux/types.h>
DECLARE_GLOBAL_DATA_PTR;
enum ath79_soc_type {
ATH79_SOC_UNKNOWN,
ATH79_SOC_AR7130,
ATH79_SOC_AR7141,
ATH79_SOC_AR7161,
ATH79_SOC_AR7240,
ATH79_SOC_AR7241,
ATH79_SOC_AR7242,
ATH79_SOC_AR9130,
ATH79_SOC_AR9132,
ATH79_SOC_AR9330,
ATH79_SOC_AR9331,
ATH79_SOC_AR9341,
ATH79_SOC_AR9342,
ATH79_SOC_AR9344,
ATH79_SOC_QCA9533,
ATH79_SOC_QCA9556,
ATH79_SOC_QCA9558,
ATH79_SOC_TP9343,
ATH79_SOC_QCA9561,
};
static inline int soc_is_ar71xx(void)
{
return gd->arch.soc == ATH79_SOC_AR7130 ||
gd->arch.soc == ATH79_SOC_AR7141 ||
gd->arch.soc == ATH79_SOC_AR7161;
}
static inline int soc_is_ar724x(void)
{
return gd->arch.soc == ATH79_SOC_AR7240 ||
gd->arch.soc == ATH79_SOC_AR7241 ||
gd->arch.soc == ATH79_SOC_AR7242;
}
static inline int soc_is_ar7240(void)
{
return gd->arch.soc == ATH79_SOC_AR7240;
}
static inline int soc_is_ar7241(void)
{
return gd->arch.soc == ATH79_SOC_AR7241;
}
static inline int soc_is_ar7242(void)
{
return gd->arch.soc == ATH79_SOC_AR7242;
}
static inline int soc_is_ar913x(void)
{
return gd->arch.soc == ATH79_SOC_AR9130 ||
gd->arch.soc == ATH79_SOC_AR9132;
}
static inline int soc_is_ar933x(void)
{
return gd->arch.soc == ATH79_SOC_AR9330 ||
gd->arch.soc == ATH79_SOC_AR9331;
}
static inline int soc_is_ar9341(void)
{
return gd->arch.soc == ATH79_SOC_AR9341;
}
static inline int soc_is_ar9342(void)
{
return gd->arch.soc == ATH79_SOC_AR9342;
}
static inline int soc_is_ar9344(void)
{
return gd->arch.soc == ATH79_SOC_AR9344;
}
static inline int soc_is_ar934x(void)
{
return soc_is_ar9341() ||
soc_is_ar9342() ||
soc_is_ar9344();
}
static inline int soc_is_qca9533(void)
{
return gd->arch.soc == ATH79_SOC_QCA9533;
}
static inline int soc_is_qca953x(void)
{
return soc_is_qca9533();
}
static inline int soc_is_qca9556(void)
{
return gd->arch.soc == ATH79_SOC_QCA9556;
}
static inline int soc_is_qca9558(void)
{
return gd->arch.soc == ATH79_SOC_QCA9558;
}
static inline int soc_is_qca955x(void)
{
return soc_is_qca9556() || soc_is_qca9558();
}
static inline int soc_is_tp9343(void)
{
return gd->arch.soc == ATH79_SOC_TP9343;
}
static inline int soc_is_qca9561(void)
{
return gd->arch.soc == ATH79_SOC_QCA9561;
}
static inline int soc_is_qca956x(void)
{
return soc_is_tp9343() || soc_is_qca9561();
}
#endif /* __ASM_MACH_ATH79_H */

13
arch/mips/mach-ath79/include/mach/ddr.h Normal file
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@ -0,0 +1,13 @@
/*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_MACH_DDR_H
#define __ASM_MACH_DDR_H
void ddr_init(void);
void ddr_tap_tuning(void);
#endif /* __ASM_MACH_DDR_H */

14
arch/mips/mach-ath79/include/mach/reset.h Normal file
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@ -0,0 +1,14 @@
/*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_MACH_RESET_H
#define __ASM_MACH_RESET_H
#include <linux/types.h>
u32 get_bootstrap(void);
#endif /* __ASM_MACH_RESET_H */

71
arch/mips/mach-ath79/reset.c Normal file
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@ -0,0 +1,71 @@
/*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ath79.h>
#include <mach/ar71xx_regs.h>
void _machine_restart(void)
{
void __iomem *base;
u32 reg = 0;
base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
MAP_NOCACHE);
if (soc_is_ar71xx())
reg = AR71XX_RESET_REG_RESET_MODULE;
else if (soc_is_ar724x())
reg = AR724X_RESET_REG_RESET_MODULE;
else if (soc_is_ar913x())
reg = AR913X_RESET_REG_RESET_MODULE;
else if (soc_is_ar933x())
reg = AR933X_RESET_REG_RESET_MODULE;
else if (soc_is_ar934x())
reg = AR934X_RESET_REG_RESET_MODULE;
else if (soc_is_qca953x())
reg = QCA953X_RESET_REG_RESET_MODULE;
else if (soc_is_qca955x())
reg = QCA955X_RESET_REG_RESET_MODULE;
else if (soc_is_qca956x())
reg = QCA956X_RESET_REG_RESET_MODULE;
else
puts("Reset register not defined for this SOC\n");
if (reg)
setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP);
while (1)
/* NOP */;
}
u32 get_bootstrap(void)
{
const void __iomem *base;
u32 reg = 0;
base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
MAP_NOCACHE);
if (soc_is_ar933x())
reg = AR933X_RESET_REG_BOOTSTRAP;
else if (soc_is_ar934x())
reg = AR934X_RESET_REG_BOOTSTRAP;
else if (soc_is_qca953x())
reg = QCA953X_RESET_REG_BOOTSTRAP;
else if (soc_is_qca955x())
reg = QCA955X_RESET_REG_BOOTSTRAP;
else if (soc_is_qca956x())
reg = QCA956X_RESET_REG_BOOTSTRAP;
else
puts("Bootstrap register not defined for this SOC\n");
if (reg)
return readl(base + reg);
return 0;
}