Marek Vasut 69ea30e688 ARM: dts: stm32: Switch to MCO2 for PHY 50 MHz clock ... The LAN8710i PHY currently uses 50 MHz clock direct from PLL4P. To permit PLL4P to run at faster frequency, use MCO2 as a divider. The PLL4P runs at 100 MHz, supplies MCO2 which divides it by 2 to 50MHz, and supplies the PHY with 50 MHz via pin PG2. The feedback clock are fed back in via pin PA1. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Change-Id: Ia9bf7119785d49b633a3ae761c3dc4a30b92628a		2021-01-13 09:52:58 +01:00
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arc	Driver model: make some udevice fields private	2021-01-05 22:34:43 -05:00
arm	ARM: dts: stm32: Switch to MCO2 for PHY 50 MHz clock	2021-01-13 09:52:58 +01:00
m68k	arc: m68k: nds32: nios2: sh: xtensa: Add empty spl.h header	2021-01-05 12:24:40 -07:00
microblaze	microblaze: Enable GCC garbage collector for full U-Boot	2020-11-20 10:42:53 +01:00
mips	Driver model: make some udevice fields private	2021-01-05 22:34:43 -05:00
nds32	arc: m68k: nds32: nios2: sh: xtensa: Add empty spl.h header	2021-01-05 12:24:40 -07:00
nios2	arc: m68k: nds32: nios2: sh: xtensa: Add empty spl.h header	2021-01-05 12:24:40 -07:00
powerpc	powerpc: mpc85xx: Allow boards to override CONFIG_USB_MAX_CONTROLLER_COUNT	2020-12-10 13:56:39 +05:30
riscv	Driver model: make some udevice fields private	2021-01-05 22:34:43 -05:00
sandbox	dm: core: add a function to decode display timings	2021-01-12 10:58:05 +05:30
sh	arc: m68k: nds32: nios2: sh: xtensa: Add empty spl.h header	2021-01-05 12:24:40 -07:00
x86	Driver model: make some udevice fields private	2021-01-05 22:34:43 -05:00
xtensa	arc: m68k: nds32: nios2: sh: xtensa: Add empty spl.h header	2021-01-05 12:24:40 -07:00
.gitignore
Kconfig	linker_lists: Fix alignment issue	2020-12-18 20:32:21 -07:00
u-boot-elf.lds	arch: Add explicit linker script for u-boot-elf	2020-04-03 11:52:55 -04:00