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https://github.com/brain-hackers/u-boot-brain
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![Marty E. Plummer](/assets/img/avatar_default.png)
This adds support for the ASUS C201, a RK3288-based clamshell device. The device tree comes from linus's linux tree at 3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters are for 4GB Samsung LPDDR3, decoded from coreboot's src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
144 lines
2.9 KiB
Plaintext
144 lines
2.9 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Veyron Speedy Rev 1+ board device tree source
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*
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* Copyright 2015 Google, Inc
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*/
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/dts-v1/;
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#include "rk3288-veyron-chromebook.dtsi"
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#include "cros-ec-sbs.dtsi"
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#include "rk3288-veyron-speedy-u-boot.dtsi"
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/ {
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model = "Google Speedy";
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compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
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"google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
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"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
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"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
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"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
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panel_regulator: panel-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&lcd_enable_h>;
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regulator-name = "panel_regulator";
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startup-delay-us = <100000>;
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vin-supply = <&vcc33_sys>;
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};
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vcc18_lcd: vcc18-lcd {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&avdd_1v8_disp_en>;
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regulator-name = "vcc18_lcd";
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vcc18_wl>;
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};
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backlight_regulator: backlight-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&bl_pwr_en>;
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regulator-name = "backlight_regulator";
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vin-supply = <&vcc33_sys>;
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startup-delay-us = <15000>;
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};
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};
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&backlight {
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power-supply = <&backlight_regulator>;
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};
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&cpu_alert0 {
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temperature = <65000>;
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};
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&cpu_alert1 {
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temperature = <70000>;
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};
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&edp {
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/delete-property/pinctrl-names;
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/delete-property/pinctrl-0;
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force-hpd;
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};
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&panel {
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power-supply = <&panel_regulator>;
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};
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&rk808 {
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_int_l>;
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};
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&sdmmc {
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disable-wp;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
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&sdmmc_bus4>;
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};
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&vcc_5v {
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enable-active-high;
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gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&drv_5v>;
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};
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&vcc50_hdmi {
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enable-active-high;
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gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc50_hdmi_en>;
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};
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&pinctrl {
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backlight {
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bl_pwr_en: bl_pwr_en {
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rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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buck-5v {
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drv_5v: drv-5v {
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rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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hdmi {
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vcc50_hdmi_en: vcc50-hdmi-en {
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rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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lcd {
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lcd_enable_h: lcd-en {
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rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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avdd_1v8_disp_en: avdd-1v8-disp-en {
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rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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pmic {
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dvs_1: dvs-1 {
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rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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dvs_2: dvs-2 {
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rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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};
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