mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-29 05:18:51 +09:00
![Lokesh Vutla](/assets/img/avatar_default.png)
Sync all AM65 related v5.11-rc6 Linux kernel dts into U-Boot. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
541 lines
12 KiB
Plaintext
541 lines
12 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-am654.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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compatible = "ti,am654-evm", "ti,am654";
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model = "Texas Instruments AM654 Base Board";
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chosen {
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stdout-path = "serial2:115200n8";
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bootargs = "earlycon=ns16550a,mmio32,0x02800000";
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};
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memory@80000000 {
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device_type = "memory";
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/* 4G RAM */
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reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
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<0x00000008 0x80000000 0x00000000 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure_ddr: secure-ddr@9e800000 {
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reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
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alignment = <0x1000>;
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no-map;
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};
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mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa0000000 0 0x100000>;
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no-map;
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};
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mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa0100000 0 0xf00000>;
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no-map;
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};
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mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa1000000 0 0x100000>;
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no-map;
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};
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mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa1100000 0 0xf00000>;
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no-map;
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};
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rtos_ipc_memory_region: ipc-memories@a2000000 {
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reg = <0x00 0xa2000000 0x00 0x00100000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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pinctrl-names = "default";
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pinctrl-0 = <&push_button_pins_default>;
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sw5 {
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label = "GPIO Key USER1";
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linux,code = <BTN_0>;
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gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
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};
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sw6 {
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label = "GPIO Key USER2";
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linux,code = <BTN_1>;
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gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
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};
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};
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clk_ov5640_fixed: clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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};
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&wkup_pmx0 {
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wkup_i2c0_pins_default: wkup-i2c0-pins-default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
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AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
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>;
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};
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push_button_pins_default: push-button-pins-default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
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AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
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>;
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};
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mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
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AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
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AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */
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AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */
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AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */
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AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */
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AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */
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AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */
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AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */
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AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
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AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
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>;
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};
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wkup_pca554_default: wkup-pca554-default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
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>;
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};
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mcu_cpsw_pins_default: mcu-cpsw-pins-default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
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AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
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AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
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AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
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AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
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AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
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AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
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AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
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AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
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AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
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AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
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AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
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>;
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};
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mcu_mdio_pins_default: mcu-mdio1-pins-default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
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AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
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>;
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};
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};
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&main_pmx0 {
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main_uart0_pins_default: main-uart0-pins-default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
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AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
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AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
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AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
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>;
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};
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main_i2c2_pins_default: main-i2c2-pins-default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */
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AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
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>;
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};
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main_spi0_pins_default: main-spi0-pins-default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
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AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
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AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */
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AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */
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>;
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};
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main_mmc0_pins_default: main-mmc0-pins-default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
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AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
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AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
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AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
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AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
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AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
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AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
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AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
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AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
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AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
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AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
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AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
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>;
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};
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main_mmc1_pins_default: main-mmc1-pins-default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
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AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
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AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
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AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
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AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
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AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
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AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
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AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
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>;
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};
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usb1_pins_default: usb1-pins-default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
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>;
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};
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};
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&main_pmx1 {
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main_i2c0_pins_default: main-i2c0-pins-default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
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AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
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>;
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};
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main_i2c1_pins_default: main-i2c1-pins-default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
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AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
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>;
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};
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ecap0_pins_default: ecap0-pins-default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
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>;
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};
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};
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&wkup_uart0 {
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/* Wakeup UART is used by System firmware */
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status = "reserved";
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};
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&main_uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart0_pins_default>;
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power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
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};
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&wkup_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&wkup_i2c0_pins_default>;
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clock-frequency = <400000>;
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pca9554: gpio@39 {
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compatible = "nxp,pca9554";
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reg = <0x39>;
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gpio-controller;
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#gpio-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&wkup_pca554_default>;
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interrupt-parent = <&wkup_gpio0>;
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interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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&main_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_pins_default>;
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clock-frequency = <400000>;
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pca9555: gpio@21 {
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compatible = "nxp,pca9555";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&main_i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c1_pins_default>;
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clock-frequency = <400000>;
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ov5640: camera@3c {
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compatible = "ovti,ov5640";
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reg = <0x3c>;
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clocks = <&clk_ov5640_fixed>;
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clock-names = "xclk";
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port {
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csi2_cam0: endpoint {
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remote-endpoint = <&csi2_phy0>;
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clock-lanes = <0>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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&main_i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c2_pins_default>;
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clock-frequency = <400000>;
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};
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&ecap0 {
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pinctrl-names = "default";
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pinctrl-0 = <&ecap0_pins_default>;
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};
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&main_spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_spi0_pins_default>;
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#address-cells = <1>;
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#size-cells= <0>;
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ti,pindir-d0-out-d1-in = <1>;
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flash@0{
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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spi-max-frequency = <48000000>;
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#address-cells = <1>;
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#size-cells= <1>;
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};
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};
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&sdhci0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_mmc0_pins_default>;
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bus-width = <8>;
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non-removable;
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ti,driver-strength-ohm = <50>;
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disable-wp;
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};
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/*
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* Because of erratas i2025 and i2026 for silicon revision 1.0, the
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* SD card interface might fail. Boards with sr1.0 are recommended to
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* disable sdhci1
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*/
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&sdhci1 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_mmc1_pins_default>;
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ti,driver-strength-ohm = <50>;
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sdhci-caps-mask = <0x7 0x0>;
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disable-wp;
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};
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&usb1 {
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pinctrl-names = "default";
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pinctrl-0 = <&usb1_pins_default>;
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dr_mode = "otg";
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};
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&dwc3_0 {
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status = "disabled";
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};
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&usb0_phy {
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status = "disabled";
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};
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&tscadc0 {
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adc {
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ti,adc-channels = <0 1 2 3 4 5 6 7>;
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};
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};
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&tscadc1 {
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adc {
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ti,adc-channels = <0 1 2 3 4 5 6 7>;
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};
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};
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&serdes0 {
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status = "disabled";
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};
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&serdes1 {
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status = "disabled";
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};
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&pcie0_rc {
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status = "disabled";
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};
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&pcie0_ep {
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status = "disabled";
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};
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&pcie1_rc {
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status = "disabled";
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};
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&pcie1_ep {
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status = "disabled";
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};
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&mailbox0_cluster0 {
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interrupts = <436>;
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mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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ti,mbox-tx = <1 0 0>;
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ti,mbox-rx = <0 0 0>;
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};
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};
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&mailbox0_cluster1 {
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interrupts = <432>;
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mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
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ti,mbox-tx = <1 0 0>;
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ti,mbox-rx = <0 0 0>;
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};
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};
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&mailbox0_cluster2 {
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status = "disabled";
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};
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&mailbox0_cluster3 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster4 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster5 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster6 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster7 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster8 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster9 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster10 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mailbox0_cluster11 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcu_r5fss0_core0 {
|
|
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
|
<&mcu_r5fss0_core0_memory_region>;
|
|
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
|
};
|
|
|
|
&mcu_r5fss0_core1 {
|
|
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
|
<&mcu_r5fss0_core1_memory_region>;
|
|
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
|
|
};
|
|
|
|
&ospi0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
|
|
|
|
flash@0{
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0x0>;
|
|
spi-tx-bus-width = <1>;
|
|
spi-rx-bus-width = <8>;
|
|
spi-max-frequency = <40000000>;
|
|
cdns,tshsl-ns = <60>;
|
|
cdns,tsd2d-ns = <60>;
|
|
cdns,tchsh-ns = <60>;
|
|
cdns,tslch-ns = <60>;
|
|
cdns,read-delay = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
};
|
|
};
|
|
|
|
&csi2_0 {
|
|
csi2_phy0: endpoint {
|
|
remote-endpoint = <&csi2_cam0>;
|
|
clock-lanes = <0>;
|
|
data-lanes = <1 2>;
|
|
};
|
|
};
|
|
|
|
&mcu_cpsw {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
|
|
};
|
|
|
|
&davinci_mdio {
|
|
phy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
|
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
|
};
|
|
};
|
|
|
|
&cpsw_port1 {
|
|
phy-mode = "rgmii-rxid";
|
|
phy-handle = <&phy0>;
|
|
};
|
|
|
|
&mcasp0 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcasp1 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&mcasp2 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&dss {
|
|
status = "disabled";
|
|
};
|