mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
arm: dts: k3-am65: Sync Linux v5.11-rc6 dts into U-Boot
Sync all AM65 related v5.11-rc6 Linux kernel dts into U-Boot. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla
parent
489274eb6c
commit
e497876343
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@ -2,13 +2,31 @@
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/*
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* Device Tree Source for AM6 SoC Family Main Domain peripherals
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*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/phy/phy-am654-serdes.h>
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#include <dt-bindings/phy/phy.h>
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&cbass_main {
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msmc_ram: sram@70000000 {
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compatible = "mmio-sram";
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reg = <0x0 0x70000000 0x0 0x200000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x70000000 0x200000>;
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atf-sram@0 {
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reg = <0x0 0x20000>;
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};
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sysfw-sram@f0000 {
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reg = <0xf0000 0x10000>;
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};
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l3cache-sram@100000 {
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reg = <0x100000 0x100000>;
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};
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};
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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@ -24,23 +42,43 @@
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*/
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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gic_its: gic-its@18200000 {
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gic_its: msi-controller@1820000 {
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compatible = "arm,gic-v3-its";
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reg = <0x00 0x01820000 0x00 0x10000>;
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socionext,synquacer-pre-its = <0x1000000 0x400000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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secure_proxy_main: mailbox@32c00000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x00 0x32c00000 0x00 0x100000>,
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<0x00 0x32400000 0x00 0x100000>,
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<0x00 0x32800000 0x00 0x100000>;
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interrupt-names = "rx_011";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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serdes0: serdes@900000 {
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compatible = "ti,phy-am654-serdes";
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reg = <0x0 0x900000 0x0 0x2000>;
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reg-names = "serdes";
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#phy-cells = <2>;
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power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
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clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
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assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
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assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
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ti,serdes-clk = <&serdes0_clk>;
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#clock-cells = <1>;
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mux-controls = <&serdes_mux 0>;
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};
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serdes1: serdes@910000 {
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compatible = "ti,phy-am654-serdes";
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reg = <0x0 0x910000 0x0 0x2000>;
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reg-names = "serdes";
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#phy-cells = <2>;
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power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
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clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
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assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
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assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
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ti,serdes-clk = <&serdes1_clk>;
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#clock-cells = <1>;
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mux-controls = <&serdes_mux 1>;
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};
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main_uart0: serial@2800000 {
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@ -51,6 +89,7 @@
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
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};
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main_uart1: serial@2810000 {
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@ -60,7 +99,7 @@
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reg-io-width = <4>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
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};
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main_uart2: serial@2820000 {
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@ -70,10 +109,31 @@
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reg-io-width = <4>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
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};
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main_pmx0: pinmux@11c000 {
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crypto: crypto@4e00000 {
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compatible = "ti,am654-sa2ul";
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reg = <0x0 0x4e00000 0x0 0x1200>;
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power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
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dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
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<&main_udmap 0x4001>;
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dma-names = "tx", "rx1", "rx2";
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dma-coherent;
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rng: rng@4e10000 {
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compatible = "inside-secure,safexcel-eip76";
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reg = <0x0 0x4e10000 0x0 0x7d>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 136 1>;
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};
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};
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main_pmx0: pinctrl@11c000 {
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compatible = "pinctrl-single";
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reg = <0x0 0x11c000 0x0 0x2e4>;
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#pinctrl-cells = <1>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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main_pmx1: pinmux@11c2e8 {
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main_pmx1: pinctrl@11c2e8 {
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compatible = "pinctrl-single";
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reg = <0x0 0x11c2e8 0x0 0x24>;
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#pinctrl-cells = <1>;
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@ -89,6 +149,113 @@
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pinctrl-single,function-mask = <0xffffffff>;
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};
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main_i2c0: i2c@2000000 {
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compatible = "ti,am654-i2c", "ti,omap4-i2c";
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reg = <0x0 0x2000000 0x0 0x100>;
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interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 110 1>;
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power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
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};
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main_i2c1: i2c@2010000 {
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compatible = "ti,am654-i2c", "ti,omap4-i2c";
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reg = <0x0 0x2010000 0x0 0x100>;
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interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 111 1>;
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power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
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};
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main_i2c2: i2c@2020000 {
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compatible = "ti,am654-i2c", "ti,omap4-i2c";
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reg = <0x0 0x2020000 0x0 0x100>;
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interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 112 1>;
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power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
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};
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main_i2c3: i2c@2030000 {
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compatible = "ti,am654-i2c", "ti,omap4-i2c";
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reg = <0x0 0x2030000 0x0 0x100>;
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interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 113 1>;
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power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
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};
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ecap0: pwm@3100000 {
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compatible = "ti,am654-ecap", "ti,am3352-ecap";
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#pwm-cells = <3>;
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reg = <0x0 0x03100000 0x0 0x60>;
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power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 39 0>;
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clock-names = "fck";
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};
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main_spi0: spi@2100000 {
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compatible = "ti,am654-mcspi","ti,omap4-mcspi";
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reg = <0x0 0x2100000 0x0 0x400>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 137 1>;
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power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
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dma-names = "tx0", "rx0";
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};
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main_spi1: spi@2110000 {
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compatible = "ti,am654-mcspi","ti,omap4-mcspi";
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reg = <0x0 0x2110000 0x0 0x400>;
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interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 138 1>;
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power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <0>;
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assigned-clocks = <&k3_clks 137 1>;
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assigned-clock-rates = <48000000>;
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};
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main_spi2: spi@2120000 {
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compatible = "ti,am654-mcspi","ti,omap4-mcspi";
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reg = <0x0 0x2120000 0x0 0x400>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 139 1>;
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power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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main_spi3: spi@2130000 {
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compatible = "ti,am654-mcspi","ti,omap4-mcspi";
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reg = <0x0 0x2130000 0x0 0x400>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 140 1>;
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power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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main_spi4: spi@2140000 {
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compatible = "ti,am654-mcspi","ti,omap4-mcspi";
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reg = <0x0 0x2140000 0x0 0x400>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 141 1>;
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power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sdhci0: sdhci@4f80000 {
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compatible = "ti,am654-sdhci-5.1";
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reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
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@ -144,64 +311,13 @@
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dma-coherent;
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};
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main_i2c0: i2c@2000000 {
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compatible = "ti,am654-i2c", "ti,omap4-i2c";
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reg = <0x0 0x2000000 0x0 0x100>;
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interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 110 1>;
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power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
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};
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main_i2c1: i2c@2010000 {
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compatible = "ti,am654-i2c", "ti,omap4-i2c";
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reg = <0x0 0x2010000 0x0 0x100>;
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interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 111 1>;
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power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
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};
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main_i2c2: i2c@2020000 {
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compatible = "ti,am654-i2c", "ti,omap4-i2c";
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reg = <0x0 0x2020000 0x0 0x100>;
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interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 112 1>;
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power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
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};
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main_i2c3: i2c@2030000 {
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compatible = "ti,am654-i2c", "ti,omap4-i2c";
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reg = <0x0 0x2030000 0x0 0x100>;
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interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 113 1>;
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power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
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};
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scm_conf: scm_conf@100000 {
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scm_conf: scm-conf@100000 {
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compatible = "syscon", "simple-mfd";
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reg = <0 0x00100000 0 0x1c000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x00100000 0x1c000>;
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serdes_mux: mux-controller {
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compatible = "mmio-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
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<0x4090 0x3>; /* SERDES1 lane select */
|
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};
|
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pcie0_mode: pcie-mode@4060 {
|
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compatible = "syscon";
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reg = <0x00004060 0x4>;
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@ -212,84 +328,37 @@
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reg = <0x00004070 0x4>;
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};
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serdes0_clk: serdes_clk@4080 {
|
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compatible = "syscon";
|
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reg = <0x00004080 0x4>;
|
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};
|
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|
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serdes1_clk: serdes_clk@4090 {
|
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compatible = "syscon";
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reg = <0x00004090 0x4>;
|
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};
|
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|
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pcie_devid: pcie-devid@210 {
|
||||
compatible = "syscon";
|
||||
reg = <0x00000210 0x4>;
|
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};
|
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};
|
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|
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serdes0: serdes@900000 {
|
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compatible = "ti,phy-am654-serdes";
|
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reg = <0x0 0x900000 0x0 0x2000>;
|
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reg-names = "serdes";
|
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#phy-cells = <2>;
|
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power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
|
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clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
|
||||
clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
|
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assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
|
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assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
|
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ti,serdes-clk = <&serdes0_clk>;
|
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mux-controls = <&serdes_mux 0>;
|
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#clock-cells = <1>;
|
||||
};
|
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serdes0_clk: clock@4080 {
|
||||
compatible = "syscon";
|
||||
reg = <0x00004080 0x4>;
|
||||
};
|
||||
|
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serdes1: serdes@910000 {
|
||||
compatible = "ti,phy-am654-serdes";
|
||||
reg = <0x0 0x910000 0x0 0x2000>;
|
||||
reg-names = "serdes";
|
||||
#phy-cells = <2>;
|
||||
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
|
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clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
|
||||
clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
|
||||
assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
|
||||
assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
|
||||
ti,serdes-clk = <&serdes1_clk>;
|
||||
mux-controls = <&serdes_mux 1>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
serdes1_clk: clock@4090 {
|
||||
compatible = "syscon";
|
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reg = <0x00004090 0x4>;
|
||||
};
|
||||
|
||||
pcie0_rc: pcie@5500000 {
|
||||
compatible = "ti,am654-pcie-rc";
|
||||
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
|
||||
reg-names = "app", "dbics", "config", "atu";
|
||||
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
|
||||
0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
|
||||
ti,syscon-pcie-id = <&pcie_devid>;
|
||||
ti,syscon-pcie-mode = <&pcie0_mode>;
|
||||
bus-range = <0x0 0xff>;
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
num-lanes = <1>;
|
||||
num-ob-windows = <16>;
|
||||
num-viewport = <16>;
|
||||
max-link-speed = <3>;
|
||||
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
|
||||
<0 0 0 2 &pcie0_intc 0>, /* INT B */
|
||||
<0 0 0 3 &pcie0_intc 0>, /* INT C */
|
||||
<0 0 0 4 &pcie0_intc 0>; /* INT D */
|
||||
msi-map = <0x0 &gic_its 0x0 0x10000>;
|
||||
serdes_mux: mux-controller {
|
||||
compatible = "mmio-mux";
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
|
||||
<0x4090 0x3>; /* SERDES1 lane select */
|
||||
};
|
||||
|
||||
pcie0_intc: legacy-interrupt-controller@1 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
|
||||
dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0000041e0 0x14>;
|
||||
};
|
||||
|
||||
ehrpwm_tbclk: clock@4140 {
|
||||
compatible = "ti,am654-ehrpwm-tbclk", "syscon";
|
||||
reg = <0x4140 0x18>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -302,6 +371,7 @@
|
|||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dma-coherent;
|
||||
power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
|
||||
assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
|
||||
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
|
||||
<&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
|
||||
|
|
@ -330,7 +400,6 @@
|
|||
clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
|
||||
clock-names = "wkupclk", "refclk";
|
||||
#phy-cells = <0>;
|
||||
ti,dis-chg-det-quirk;
|
||||
};
|
||||
|
||||
dwc3_1: dwc3@4020000 {
|
||||
|
|
@ -342,6 +411,7 @@
|
|||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dma-coherent;
|
||||
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 152 2>;
|
||||
assigned-clocks = <&k3_clks 152 2>;
|
||||
assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
|
||||
|
||||
|
|
@ -368,6 +438,492 @@
|
|||
clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
|
||||
clock-names = "wkupclk", "refclk";
|
||||
#phy-cells = <0>;
|
||||
ti,dis-chg-det-quirk;
|
||||
};
|
||||
|
||||
intr_main_gpio: interrupt-controller0 {
|
||||
compatible = "ti,sci-intr";
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <100>;
|
||||
ti,interrupt-ranges = <0 392 32>;
|
||||
};
|
||||
|
||||
main-navss {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
ti,sci-dev-id = <118>;
|
||||
|
||||
intr_main_navss: interrupt-controller1 {
|
||||
compatible = "ti,sci-intr";
|
||||
ti,intr-trigger-type = <4>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <182>;
|
||||
ti,interrupt-ranges = <0 64 64>,
|
||||
<64 448 64>;
|
||||
};
|
||||
|
||||
inta_main_udmass: interrupt-controller@33d00000 {
|
||||
compatible = "ti,sci-inta";
|
||||
reg = <0x0 0x33d00000 0x0 0x100000>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
msi-controller;
|
||||
#interrupt-cells = <0>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <179>;
|
||||
ti,interrupt-ranges = <0 0 256>;
|
||||
};
|
||||
|
||||
secure_proxy_main: mailbox@32c00000 {
|
||||
compatible = "ti,am654-secure-proxy";
|
||||
#mbox-cells = <1>;
|
||||
reg-names = "target_data", "rt", "scfg";
|
||||
reg = <0x00 0x32c00000 0x00 0x100000>,
|
||||
<0x00 0x32400000 0x00 0x100000>,
|
||||
<0x00 0x32800000 0x00 0x100000>;
|
||||
interrupt-names = "rx_011";
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
hwspinlock: spinlock@30e00000 {
|
||||
compatible = "ti,am654-hwspinlock";
|
||||
reg = <0x00 0x30e00000 0x00 0x1000>;
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
mailbox0_cluster0: mailbox@31f80000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f80000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
};
|
||||
|
||||
mailbox0_cluster1: mailbox@31f81000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f81000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
};
|
||||
|
||||
mailbox0_cluster2: mailbox@31f82000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f82000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
};
|
||||
|
||||
mailbox0_cluster3: mailbox@31f83000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f83000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
};
|
||||
|
||||
mailbox0_cluster4: mailbox@31f84000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f84000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
};
|
||||
|
||||
mailbox0_cluster5: mailbox@31f85000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f85000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
};
|
||||
|
||||
mailbox0_cluster6: mailbox@31f86000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f86000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
};
|
||||
|
||||
mailbox0_cluster7: mailbox@31f87000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f87000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
};
|
||||
|
||||
mailbox0_cluster8: mailbox@31f88000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f88000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
};
|
||||
|
||||
mailbox0_cluster9: mailbox@31f89000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f89000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
};
|
||||
|
||||
mailbox0_cluster10: mailbox@31f8a000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f8a000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
};
|
||||
|
||||
mailbox0_cluster11: mailbox@31f8b000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x00 0x31f8b000 0x00 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
interrupt-parent = <&intr_main_navss>;
|
||||
};
|
||||
|
||||
ringacc: ringacc@3c000000 {
|
||||
compatible = "ti,am654-navss-ringacc";
|
||||
reg = <0x0 0x3c000000 0x0 0x400000>,
|
||||
<0x0 0x38000000 0x0 0x400000>,
|
||||
<0x0 0x31120000 0x0 0x100>,
|
||||
<0x0 0x33000000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||
ti,num-rings = <818>;
|
||||
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <187>;
|
||||
msi-parent = <&inta_main_udmass>;
|
||||
};
|
||||
|
||||
main_udmap: dma-controller@31150000 {
|
||||
compatible = "ti,am654-navss-main-udmap";
|
||||
reg = <0x0 0x31150000 0x0 0x100>,
|
||||
<0x0 0x34000000 0x0 0x100000>,
|
||||
<0x0 0x35000000 0x0 0x100000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt";
|
||||
msi-parent = <&inta_main_udmass>;
|
||||
#dma-cells = <1>;
|
||||
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <188>;
|
||||
ti,ringacc = <&ringacc>;
|
||||
|
||||
ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
|
||||
<0xd>; /* TX_CHAN */
|
||||
ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
|
||||
<0xa>; /* RX_CHAN */
|
||||
ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
|
||||
};
|
||||
|
||||
cpts@310d0000 {
|
||||
compatible = "ti,am65-cpts";
|
||||
reg = <0x0 0x310d0000 0x0 0x400>;
|
||||
reg-names = "cpts";
|
||||
clocks = <&main_cpts_mux>;
|
||||
clock-names = "cpts";
|
||||
interrupts-extended = <&intr_main_navss 391>;
|
||||
interrupt-names = "cpts";
|
||||
ti,cpts-periodic-outputs = <6>;
|
||||
ti,cpts-ext-ts-inputs = <8>;
|
||||
|
||||
main_cpts_mux: refclk-mux {
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
|
||||
<&k3_clks 118 6>, <&k3_clks 118 3>,
|
||||
<&k3_clks 118 8>, <&k3_clks 118 14>,
|
||||
<&k3_clks 120 3>, <&k3_clks 121 3>;
|
||||
assigned-clocks = <&main_cpts_mux>;
|
||||
assigned-clock-parents = <&k3_clks 118 5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
main_gpio0: gpio@600000 {
|
||||
compatible = "ti,am654-gpio", "ti,keystone-gpio";
|
||||
reg = <0x0 0x600000 0x0 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&intr_main_gpio>;
|
||||
interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <96>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
clocks = <&k3_clks 57 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_gpio1: gpio@601000 {
|
||||
compatible = "ti,am654-gpio", "ti,keystone-gpio";
|
||||
reg = <0x0 0x601000 0x0 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&intr_main_gpio>;
|
||||
interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <90>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
clocks = <&k3_clks 58 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
pcie0_rc: pcie@5500000 {
|
||||
compatible = "ti,am654-pcie-rc";
|
||||
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
|
||||
reg-names = "app", "dbics", "config", "atu";
|
||||
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
|
||||
0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
|
||||
ti,syscon-pcie-id = <&pcie_devid>;
|
||||
ti,syscon-pcie-mode = <&pcie0_mode>;
|
||||
bus-range = <0x0 0xff>;
|
||||
num-viewport = <16>;
|
||||
max-link-speed = <2>;
|
||||
dma-coherent;
|
||||
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
|
||||
msi-map = <0x0 &gic_its 0x0 0x10000>;
|
||||
};
|
||||
|
||||
pcie0_ep: pcie-ep@5500000 {
|
||||
compatible = "ti,am654-pcie-ep";
|
||||
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
|
||||
reg-names = "app", "dbics", "addr_space", "atu";
|
||||
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,syscon-pcie-mode = <&pcie0_mode>;
|
||||
num-ib-windows = <16>;
|
||||
num-ob-windows = <16>;
|
||||
max-link-speed = <2>;
|
||||
dma-coherent;
|
||||
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
pcie1_rc: pcie@5600000 {
|
||||
compatible = "ti,am654-pcie-rc";
|
||||
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
|
||||
reg-names = "app", "dbics", "config", "atu";
|
||||
power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
|
||||
0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
|
||||
ti,syscon-pcie-id = <&pcie_devid>;
|
||||
ti,syscon-pcie-mode = <&pcie1_mode>;
|
||||
bus-range = <0x0 0xff>;
|
||||
num-viewport = <16>;
|
||||
max-link-speed = <2>;
|
||||
dma-coherent;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
|
||||
msi-map = <0x0 &gic_its 0x10000 0x10000>;
|
||||
};
|
||||
|
||||
pcie1_ep: pcie-ep@5600000 {
|
||||
compatible = "ti,am654-pcie-ep";
|
||||
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
|
||||
reg-names = "app", "dbics", "addr_space", "atu";
|
||||
power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
|
||||
ti,syscon-pcie-mode = <&pcie1_mode>;
|
||||
num-ib-windows = <16>;
|
||||
num-ob-windows = <16>;
|
||||
max-link-speed = <2>;
|
||||
dma-coherent;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
mcasp0: mcasp@2b00000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x0 0x02b00000 0x0 0x2000>,
|
||||
<0x0 0x02b08000 0x0 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
|
||||
dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
clocks = <&k3_clks 104 0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
mcasp1: mcasp@2b10000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x0 0x02b10000 0x0 0x2000>,
|
||||
<0x0 0x02b18000 0x0 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
|
||||
dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
clocks = <&k3_clks 105 0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
mcasp2: mcasp@2b20000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
reg = <0x0 0x02b20000 0x0 0x2000>,
|
||||
<0x0 0x02b28000 0x0 0x1000>;
|
||||
reg-names = "mpu","dat";
|
||||
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tx", "rx";
|
||||
|
||||
dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
clocks = <&k3_clks 106 0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
cal: cal@6f03000 {
|
||||
compatible = "ti,am654-cal";
|
||||
reg = <0x0 0x06f03000 0x0 0x400>,
|
||||
<0x0 0x06f03800 0x0 0x40>;
|
||||
reg-names = "cal_top",
|
||||
"cal_rx_core0";
|
||||
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,camerrx-control = <&scm_conf 0x40c0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 2 0>;
|
||||
power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csi2_0: port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dss: dss@4a00000 {
|
||||
compatible = "ti,am65x-dss";
|
||||
reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
|
||||
<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
|
||||
<0x0 0x04a06000 0x0 0x1000>, /* vid */
|
||||
<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
|
||||
<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
|
||||
<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
|
||||
<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
|
||||
reg-names = "common", "vidl1", "vid",
|
||||
"ovr1", "ovr2", "vp1", "vp2";
|
||||
|
||||
ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
|
||||
|
||||
power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
clocks = <&k3_clks 67 1>,
|
||||
<&k3_clks 216 1>,
|
||||
<&k3_clks 67 2>;
|
||||
clock-names = "fck", "vp1", "vp2";
|
||||
|
||||
/*
|
||||
* Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
|
||||
* DIV1. See "Figure 12-3365. DSS Integration"
|
||||
* in AM65x TRM for details.
|
||||
*/
|
||||
assigned-clocks = <&k3_clks 67 2>;
|
||||
assigned-clock-parents = <&k3_clks 67 5>;
|
||||
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
dma-coherent;
|
||||
|
||||
dss_ports: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ehrpwm0: pwm@3000000 {
|
||||
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x0 0x3000000 0x0 0x100>;
|
||||
power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
};
|
||||
|
||||
ehrpwm1: pwm@3010000 {
|
||||
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x0 0x3010000 0x0 0x100>;
|
||||
power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
};
|
||||
|
||||
ehrpwm2: pwm@3020000 {
|
||||
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x0 0x3020000 0x0 0x100>;
|
||||
power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
};
|
||||
|
||||
ehrpwm3: pwm@3030000 {
|
||||
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x0 0x3030000 0x0 0x100>;
|
||||
power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
};
|
||||
|
||||
ehrpwm4: pwm@3040000 {
|
||||
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x0 0x3040000 0x0 0x100>;
|
||||
power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
};
|
||||
|
||||
ehrpwm5: pwm@3050000 {
|
||||
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x0 0x3050000 0x0 0x100>;
|
||||
power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,11 +2,11 @@
|
|||
/*
|
||||
* Device Tree Source for AM6 SoC Family MCU Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_mcu {
|
||||
mcu_conf: scm_conf@40f00000 {
|
||||
mcu_conf: scm-conf@40f00000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x0 0x40f00000 0x0 0x20000>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -28,6 +28,15 @@
|
|||
interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <96000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
mcu_ram: sram@41c00000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00 0x41c00000 0x00 0x80000>;
|
||||
ranges = <0x0 0x00 0x41c00000 0x80000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
mcu_i2c0: i2c@40b00000 {
|
||||
|
|
@ -41,41 +50,114 @@
|
|||
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
mcu_r5fss0: r5fss@41000000 {
|
||||
compatible = "ti,am654-r5fss";
|
||||
ti,cluster-mode = <0>;
|
||||
mcu_spi0: spi@40300000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x0 0x40300000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 142 1>;
|
||||
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x41000000 0x00 0x41000000 0x20000>,
|
||||
<0x41400000 0x00 0x41400000 0x20000>;
|
||||
power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0: r5f@41000000 {
|
||||
compatible = "ti,am654-r5f";
|
||||
reg = <0x41000000 0x00008000>,
|
||||
<0x41010000 0x00008000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
mcu_spi1: spi@40310000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x0 0x40310000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 143 1>;
|
||||
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mcu_spi2: spi@40320000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x0 0x40320000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 144 1>;
|
||||
power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
tscadc0: tscadc@40200000 {
|
||||
compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
|
||||
reg = <0x0 0x40200000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 0 2>;
|
||||
assigned-clocks = <&k3_clks 0 2>;
|
||||
assigned-clock-rates = <60000000>;
|
||||
clock-names = "adc_tsc_fck";
|
||||
dmas = <&mcu_udmap 0x7100>,
|
||||
<&mcu_udmap 0x7101 >;
|
||||
dma-names = "fifo0", "fifo1";
|
||||
|
||||
adc {
|
||||
#io-channel-cells = <1>;
|
||||
compatible = "ti,am654-adc", "ti,am3359-adc";
|
||||
};
|
||||
};
|
||||
|
||||
tscadc1: tscadc@40210000 {
|
||||
compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
|
||||
reg = <0x0 0x40210000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 1 2>;
|
||||
assigned-clocks = <&k3_clks 1 2>;
|
||||
assigned-clock-rates = <60000000>;
|
||||
clock-names = "adc_tsc_fck";
|
||||
dmas = <&mcu_udmap 0x7102>,
|
||||
<&mcu_udmap 0x7103>;
|
||||
dma-names = "fifo0", "fifo1";
|
||||
|
||||
adc {
|
||||
#io-channel-cells = <1>;
|
||||
compatible = "ti,am654-adc", "ti,am3359-adc";
|
||||
};
|
||||
};
|
||||
|
||||
mcu-navss {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
ti,sci-dev-id = <119>;
|
||||
|
||||
mcu_ringacc: ringacc@2b800000 {
|
||||
compatible = "ti,am654-navss-ringacc";
|
||||
reg = <0x0 0x2b800000 0x0 0x400000>,
|
||||
<0x0 0x2b000000 0x0 0x400000>,
|
||||
<0x0 0x28590000 0x0 0x100>,
|
||||
<0x0 0x2a500000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||
ti,num-rings = <286>;
|
||||
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <159>;
|
||||
ti,sci-proc-ids = <0x01 0xFF>;
|
||||
resets = <&k3_reset 159 1>;
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
ti,sci-dev-id = <195>;
|
||||
msi-parent = <&inta_main_udmass>;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1: r5f@41400000 {
|
||||
compatible = "ti,am654-r5f";
|
||||
reg = <0x41400000 0x00008000>,
|
||||
<0x41410000 0x00008000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
mcu_udmap: dma-controller@285c0000 {
|
||||
compatible = "ti,am654-navss-mcu-udmap";
|
||||
reg = <0x0 0x285c0000 0x0 0x100>,
|
||||
<0x0 0x2a800000 0x0 0x40000>,
|
||||
<0x0 0x2aa00000 0x0 0x40000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt";
|
||||
msi-parent = <&inta_main_udmass>;
|
||||
#dma-cells = <1>;
|
||||
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <245>;
|
||||
ti,sci-proc-ids = <0x02 0xFF>;
|
||||
resets = <&k3_reset 245 1>;
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
ti,sci-dev-id = <194>;
|
||||
ti,ringacc = <&mcu_ringacc>;
|
||||
|
||||
ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
|
||||
<0xd>; /* TX_CHAN */
|
||||
ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
|
||||
<0xa>; /* RX_CHAN */
|
||||
ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -117,50 +199,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
mcu_navss {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
ti,sci-dev-id = <119>;
|
||||
|
||||
mcu_ringacc: ringacc@2b800000 {
|
||||
compatible = "ti,am654-navss-ringacc";
|
||||
reg = <0x0 0x2b800000 0x0 0x400000>,
|
||||
<0x0 0x2b000000 0x0 0x400000>,
|
||||
<0x0 0x28590000 0x0 0x100>,
|
||||
<0x0 0x2a500000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||
ti,num-rings = <286>;
|
||||
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||
ti,dma-ring-reset-quirk;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <195>;
|
||||
};
|
||||
|
||||
mcu_udmap: dma-controller@285c0000 {
|
||||
compatible = "ti,am654-navss-mcu-udmap";
|
||||
reg = <0x0 0x285c0000 0x0 0x100>,
|
||||
<0x0 0x2a800000 0x0 0x40000>,
|
||||
<0x0 0x2aa00000 0x0 0x40000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt";
|
||||
#dma-cells = <1>;
|
||||
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <194>;
|
||||
ti,ringacc = <&mcu_ringacc>;
|
||||
|
||||
ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
|
||||
<0xd>; /* TX_CHAN */
|
||||
ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
|
||||
<0xa>; /* RX_CHAN */
|
||||
ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
|
||||
};
|
||||
};
|
||||
|
||||
mcu_cpsw: ethernet@46000000 {
|
||||
compatible = "ti,am654-cpsw-nuss";
|
||||
#address-cells = <2>;
|
||||
|
|
@ -231,12 +269,43 @@
|
|||
};
|
||||
};
|
||||
|
||||
mcu_rti1: rti@40610000 {
|
||||
compatible = "ti,j7-rti-wdt";
|
||||
reg = <0x0 0x40610000 0x0 0x100>;
|
||||
clocks = <&k3_clks 135 0>;
|
||||
power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
|
||||
assigned-clocks = <&k3_clks 135 0>;
|
||||
assigned-clock-parents = <&k3_clks 135 4>;
|
||||
mcu_r5fss0: r5fss@41000000 {
|
||||
compatible = "ti,am654-r5fss";
|
||||
ti,cluster-mode = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x41000000 0x00 0x41000000 0x20000>,
|
||||
<0x41400000 0x00 0x41400000 0x20000>;
|
||||
power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
mcu_r5fss0_core0: r5f@41000000 {
|
||||
compatible = "ti,am654-r5f";
|
||||
reg = <0x41000000 0x00008000>,
|
||||
<0x41010000 0x00008000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <159>;
|
||||
ti,sci-proc-ids = <0x01 0xff>;
|
||||
resets = <&k3_reset 159 1>;
|
||||
firmware-name = "am65x-mcu-r5f0_0-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1: r5f@41400000 {
|
||||
compatible = "ti,am654-r5f";
|
||||
reg = <0x41400000 0x00008000>,
|
||||
<0x41410000 0x00008000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <245>;
|
||||
ti,sci-proc-ids = <0x02 0xff>;
|
||||
resets = <&k3_reset 245 1>;
|
||||
firmware-name = "am65x-mcu-r5f0_1-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Device Tree Source for AM6 SoC Family Wakeup Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_wakeup {
|
||||
|
|
@ -34,7 +34,12 @@
|
|||
};
|
||||
};
|
||||
|
||||
wkup_pmx0: pinmux@4301c000 {
|
||||
chipid@43000014 {
|
||||
compatible = "ti,am654-chipid";
|
||||
reg = <0x43000014 0x4>;
|
||||
};
|
||||
|
||||
wkup_pmx0: pinctrl@4301c000 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x4301c000 0x118>;
|
||||
#pinctrl-cells = <1>;
|
||||
|
|
@ -50,6 +55,7 @@
|
|||
interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
wkup_i2c0: i2c@42120000 {
|
||||
|
|
@ -63,8 +69,40 @@
|
|||
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
chipid: chipid@43000014 {
|
||||
compatible = "ti,am654-chipid";
|
||||
reg = <0x43000014 0x4>;
|
||||
intr_wkup_gpio: interrupt-controller2 {
|
||||
compatible = "ti,sci-intr";
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <156>;
|
||||
ti,interrupt-ranges = <0 712 16>;
|
||||
};
|
||||
|
||||
wkup_gpio0: gpio@42110000 {
|
||||
compatible = "ti,am654-gpio", "ti,keystone-gpio";
|
||||
reg = <0x42110000 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&intr_wkup_gpio>;
|
||||
interrupts = <60>, <61>, <62>, <63>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <56>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
clocks = <&k3_clks 59 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
wkup_vtm0: temperature-sensor@42050000 {
|
||||
compatible = "ti,am654-vtm";
|
||||
reg = <0x42050000 0x25c>;
|
||||
power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
thermal_zones: thermal-zones {
|
||||
#include "k3-am654-industrial-thermal.dtsi"
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Device Tree Source for AM6 SoC Family
|
||||
*
|
||||
* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
|
@ -30,8 +30,7 @@
|
|||
i2c3 = &main_i2c1;
|
||||
i2c4 = &main_i2c2;
|
||||
i2c5 = &main_i2c3;
|
||||
spi0 = &ospi0;
|
||||
spi1 = &ospi1;
|
||||
ethernet0 = &cpsw_port1;
|
||||
};
|
||||
|
||||
chosen { };
|
||||
|
|
@ -71,13 +70,15 @@
|
|||
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
|
||||
<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
|
||||
<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
|
||||
/* MCUSS Range */
|
||||
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
|
||||
|
|
@ -96,6 +97,7 @@
|
|||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
|
||||
|
|
|
|||
|
|
@ -16,21 +16,27 @@
|
|||
ethernet0 = &cpsw_port1;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
spi0 = &ospi0;
|
||||
spi1 = &ospi1;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_main{
|
||||
u-boot,dm-spl;
|
||||
main-navss {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_mcu {
|
||||
u-boot,dm-spl;
|
||||
|
||||
mcu_navss {
|
||||
mcu-navss {
|
||||
u-boot,dm-spl;
|
||||
|
||||
ringacc@2b800000 {
|
||||
u-boot,dm-spl;
|
||||
ti,dma-ring-reset-quirk;
|
||||
};
|
||||
|
||||
dma-controller@285c0000 {
|
||||
|
|
@ -41,6 +47,10 @@
|
|||
|
||||
&cbass_wakeup {
|
||||
u-boot,dm-spl;
|
||||
|
||||
chipid@43000014 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&secure_proxy_main {
|
||||
|
|
@ -77,16 +87,6 @@
|
|||
|
||||
&main_pmx0 {
|
||||
u-boot,dm-spl;
|
||||
main_uart0_pins_default: main_uart0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
|
||||
AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
|
||||
AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
|
||||
AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
|
||||
>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
usb0_pins_default: usb0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
|
||||
|
|
@ -95,35 +95,15 @@
|
|||
};
|
||||
};
|
||||
|
||||
&main_uart0_pins_default {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&main_pmx1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
mcu_cpsw_pins_default: mcu_cpsw_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
|
||||
AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
|
||||
AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
|
||||
AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
|
||||
AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
|
||||
AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
|
||||
AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
|
||||
AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
|
||||
AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
|
||||
AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
|
||||
AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
|
||||
AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_mdio_pins_default: mcu_mdio1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
|
||||
AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu-fss0-ospi0-pins-default {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
@ -131,9 +111,6 @@
|
|||
|
||||
&main_uart0 {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_mmc0_pins_default {
|
||||
|
|
@ -152,11 +129,6 @@
|
|||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&mcu_cpsw {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
|
|
@ -166,11 +138,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
&mcu_cpsw {
|
||||
reg = <0x0 0x46000000 0x0 0x200000>,
|
||||
<0x0 0x40f00200 0x0 0x2>;
|
||||
|
|
@ -204,10 +171,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&chipid {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
u-boot,dm-spl;
|
||||
|
|
|
|||
|
|
@ -1,12 +1,13 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am654.dtsi"
|
||||
#include <dt-bindings/pinctrl/k3.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
|
||||
/ {
|
||||
compatible = "ti,am654-evm", "ti,am654";
|
||||
|
|
@ -17,11 +18,6 @@
|
|||
bootargs = "earlycon=ns16550a,mmio32,0x02800000";
|
||||
};
|
||||
|
||||
aliases {
|
||||
remoteproc0 = &mcu_r5fss0_core0;
|
||||
remoteproc1 = &mcu_r5fss0_core1;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 4G RAM */
|
||||
|
|
@ -33,48 +29,139 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
secure_ddr: secure_ddr@9e800000 {
|
||||
|
||||
secure_ddr: secure-ddr@9e800000 {
|
||||
reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa0000000 0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa0100000 0 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa1000000 0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa1100000 0 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a2000000 {
|
||||
reg = <0x00 0xa2000000 0x00 0x00100000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&push_button_pins_default>;
|
||||
|
||||
sw5 {
|
||||
label = "GPIO Key USER1";
|
||||
linux,code = <BTN_0>;
|
||||
gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
sw6 {
|
||||
label = "GPIO Key USER2";
|
||||
linux,code = <BTN_1>;
|
||||
gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
clk_ov5640_fixed: clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
|
||||
AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
push_button_pins_default: push-button-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
|
||||
AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
|
||||
AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
|
||||
AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */
|
||||
AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */
|
||||
AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */
|
||||
AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */
|
||||
AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */
|
||||
AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */
|
||||
AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */
|
||||
AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
|
||||
AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
|
||||
>;
|
||||
};
|
||||
|
||||
wkup_pca554_default: wkup-pca554-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
|
||||
AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
|
||||
AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
|
||||
AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
|
||||
AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
|
||||
AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
|
||||
AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
|
||||
AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
|
||||
AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
|
||||
AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
|
||||
AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
|
||||
AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_mdio_pins_default: mcu-mdio1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
|
||||
AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_mmc0_pins_default: main_mmc0_pins_default {
|
||||
main_uart0_pins_default: main-uart0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
|
||||
AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
|
||||
AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
|
||||
AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
|
||||
AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
|
||||
AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
|
||||
AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
|
||||
AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
|
||||
AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
|
||||
AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
|
||||
AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
|
||||
AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main_mmc1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
|
||||
AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
|
||||
AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
|
||||
AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
|
||||
AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
|
||||
AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
|
||||
AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
|
||||
AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
|
||||
>;
|
||||
};
|
||||
|
||||
usb1_pins_default: usb1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
|
||||
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
|
||||
AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
|
||||
AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
|
||||
AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -84,6 +171,51 @@
|
|||
AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_spi0_pins_default: main-spi0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
|
||||
AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
|
||||
AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */
|
||||
AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc0_pins_default: main-mmc0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
|
||||
AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
|
||||
AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
|
||||
AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
|
||||
AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
|
||||
AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
|
||||
AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
|
||||
AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
|
||||
AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
|
||||
AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
|
||||
AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
|
||||
AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
|
||||
AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
|
||||
AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
|
||||
AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
|
||||
AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
|
||||
AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
|
||||
AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
|
||||
AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
|
||||
>;
|
||||
};
|
||||
|
||||
usb1_pins_default: usb1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx1 {
|
||||
|
|
@ -100,52 +232,23 @@
|
|||
AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
|
||||
ecap0_pins_default: ecap0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
|
||||
AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
|
||||
AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
|
||||
AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */
|
||||
AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */
|
||||
AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */
|
||||
AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */
|
||||
AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */
|
||||
AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */
|
||||
AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */
|
||||
AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
|
||||
AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
|
||||
AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc0_pins_default>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
&wkup_uart0 {
|
||||
/* Wakeup UART is used by System firmware */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
/*
|
||||
* Because of erratas i2025 and i2026 for silicon revision 1.0, the
|
||||
* SD card interface might fail. Boards with sr1.0 are recommended to
|
||||
* disable sdhci1
|
||||
*/
|
||||
&sdhci1 {
|
||||
&main_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
sdhci-caps-mask = <0x7 0x0>;
|
||||
disable-wp;
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
|
||||
};
|
||||
|
||||
&wkup_i2c0 {
|
||||
|
|
@ -153,11 +256,17 @@
|
|||
pinctrl-0 = <&wkup_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tca9554: gpio@38 {
|
||||
pca9554: gpio@39 {
|
||||
compatible = "nxp,pca9554";
|
||||
reg = <0x38>;
|
||||
reg = <0x39>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_pca554_default>;
|
||||
interrupt-parent = <&wkup_gpio0>;
|
||||
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -178,6 +287,23 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
ov5640: camera@3c {
|
||||
compatible = "ovti,ov5640";
|
||||
reg = <0x3c>;
|
||||
|
||||
clocks = <&clk_ov5640_fixed>;
|
||||
clock-names = "xclk";
|
||||
|
||||
port {
|
||||
csi2_cam0: endpoint {
|
||||
remote-endpoint = <&csi2_phy0>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&main_i2c2 {
|
||||
|
|
@ -186,12 +312,49 @@
|
|||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&dwc3_1 {
|
||||
status = "okay";
|
||||
&ecap0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ecap0_pins_default>;
|
||||
};
|
||||
|
||||
&usb1_phy {
|
||||
status = "okay";
|
||||
&main_spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_spi0_pins_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells= <0>;
|
||||
ti,pindir-d0-out-d1-in = <1>;
|
||||
|
||||
flash@0{
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <1>;
|
||||
spi-max-frequency = <48000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells= <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc0_pins_default>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
/*
|
||||
* Because of erratas i2025 and i2026 for silicon revision 1.0, the
|
||||
* SD card interface might fail. Boards with sr1.0 are recommended to
|
||||
* disable sdhci1
|
||||
*/
|
||||
&sdhci1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
sdhci-caps-mask = <0x7 0x0>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
|
|
@ -208,6 +371,112 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&tscadc0 {
|
||||
adc {
|
||||
ti,adc-channels = <0 1 2 3 4 5 6 7>;
|
||||
};
|
||||
};
|
||||
|
||||
&tscadc1 {
|
||||
adc {
|
||||
ti,adc-channels = <0 1 2 3 4 5 6 7>;
|
||||
};
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&serdes1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie0_rc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie0_ep {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie1_rc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie1_ep {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster7 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster8 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster9 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster10 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster11 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
|
||||
|
|
@ -217,7 +486,7 @@
|
|||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-max-frequency = <40000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
|
|
@ -227,3 +496,45 @@
|
|||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&csi2_0 {
|
||||
csi2_phy0: endpoint {
|
||||
remote-endpoint = <&csi2_cam0>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_cpsw {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
&mcasp0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcasp1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcasp2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
45
arch/arm/dts/k3-am654-industrial-thermal.dtsi
Normal file
45
arch/arm/dts/k3-am654-industrial-thermal.dtsi
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
mpu0_thermal: mpu0-thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
thermal-sensors = <&wkup_vtm0 0>;
|
||||
|
||||
trips {
|
||||
mpu0_crit: mpu0-crit {
|
||||
temperature = <125000>; /* milliCelsius */
|
||||
hysteresis = <2000>; /* milliCelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mpu1_thermal: mpu1-thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
thermal-sensors = <&wkup_vtm0 1>;
|
||||
|
||||
trips {
|
||||
mpu1_crit: mpu1-crit {
|
||||
temperature = <125000>; /* milliCelsius */
|
||||
hysteresis = <2000>; /* milliCelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mcu_thermal: mcu-thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
thermal-sensors = <&wkup_vtm0 2>;
|
||||
|
||||
trips {
|
||||
mcu_crit: mcu-crit {
|
||||
temperature = <125000>; /* milliCelsius */
|
||||
hysteresis = <2000>; /* milliCelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -77,6 +77,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&wkup_gpio0 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&cbass_wakeup {
|
||||
sysctrler: sysctrler {
|
||||
compatible = "ti,am654-system-controller";
|
||||
|
|
@ -85,25 +89,6 @@
|
|||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
wkup_gpio0: wkup_gpio0@42110000 {
|
||||
compatible = "ti,k2g-gpio", "ti,keystone-gpio";
|
||||
reg = <0x42110000 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ti,ngpio = <56>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
clocks = <&k3_clks 59 0>;
|
||||
clock-names = "gpio";
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
wkup_vtm0: wkup_vtm@42050000 {
|
||||
compatible = "ti,am654-vtm", "ti,am654-avs";
|
||||
reg = <0x42050000 0x25c>;
|
||||
power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
clk_200mhz: dummy_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
|
|
@ -131,14 +116,19 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_uart0_pins_default>;
|
||||
clock-frequency = <48000000>;
|
||||
/delete-property/ power-domains;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_vtm0 {
|
||||
compatible = "ti,am654-vtm", "ti,am654-avs";
|
||||
vdd-supply-3 = <&vdd_mpu>;
|
||||
vdd-supply-4 = <&vdd_mpu>;
|
||||
u-boot,dm-spl;
|
||||
|
|
@ -199,6 +189,16 @@
|
|||
|
||||
&main_pmx0 {
|
||||
u-boot,dm-spl;
|
||||
main_uart0_pins_default: main-uart0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
|
||||
AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
|
||||
AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
|
||||
AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
|
||||
>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
main_mmc0_pins_default: main_mmc0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Device Tree Source for AM6 SoC family in Quad core configuration
|
||||
*
|
||||
* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include "k3-am65.dtsi"
|
||||
|
|
@ -34,7 +34,7 @@
|
|||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
|
|
@ -48,7 +48,7 @@
|
|||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
|
|
@ -62,7 +62,7 @@
|
|||
};
|
||||
|
||||
cpu2: cpu@100 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
|
|
@ -76,7 +76,7 @@
|
|||
};
|
||||
|
||||
cpu3: cpu@101 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x101>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user