mirror of
https://github.com/brain-hackers/u-boot-brain
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629d6b32d6
Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
92 lines
2.6 KiB
C
92 lines
2.6 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* Shengzhou Liu <Shengzhou.Liu@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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u32 port_to_devdisr[] = {
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[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
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[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
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[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
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[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
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[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
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[FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
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[FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
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[FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
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[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
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[FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
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[FM1_10GEC3] = FSL_CORENET_DEVDISR2_10GEC1_3,
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[FM1_10GEC4] = FSL_CORENET_DEVDISR2_10GEC1_4,
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};
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static int is_device_disabled(enum fm_port port)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 devdisr2 = in_be32(&gur->devdisr2);
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return port_to_devdisr[port] & devdisr2;
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}
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void fman_disable_port(enum fm_port port)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
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}
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phy_interface_t fman_port_enet_if(enum fm_port port)
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
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if (is_device_disabled(port))
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return PHY_INTERFACE_MODE_NONE;
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if ((port == FM1_10GEC1 || port == FM1_10GEC2 ||
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port == FM1_10GEC3 || port == FM1_10GEC4) &&
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((is_serdes_configured(XAUI_FM1_MAC9)) ||
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(is_serdes_configured(XFI_FM1_MAC1)) ||
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(is_serdes_configured(XFI_FM1_MAC2)) ||
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(is_serdes_configured(XFI_FM1_MAC9)) ||
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(is_serdes_configured(XFI_FM1_MAC10))))
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return PHY_INTERFACE_MODE_XGMII;
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if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
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FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII))
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return PHY_INTERFACE_MODE_RGMII;
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if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
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FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII))
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return PHY_INTERFACE_MODE_RGMII;
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if ((port == FM1_DTSEC10) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
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FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII))
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return PHY_INTERFACE_MODE_RGMII;
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switch (port) {
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case FM1_DTSEC1:
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case FM1_DTSEC2:
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case FM1_DTSEC3:
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case FM1_DTSEC4:
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case FM1_DTSEC5:
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case FM1_DTSEC6:
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case FM1_DTSEC9:
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case FM1_DTSEC10:
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if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
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return PHY_INTERFACE_MODE_SGMII;
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break;
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default:
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return PHY_INTERFACE_MODE_NONE;
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}
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return PHY_INTERFACE_MODE_NONE;
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}
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