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The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
579 lines
21 KiB
C
579 lines
21 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/**********************************************************************
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* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
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**********************************************************************
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* WARNING: This file is auto-generated using api-generator utility.
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* api-generator: 12.02.13bb8d5
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* Do not edit it manually.
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**********************************************************************
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* Cadence Core Driver for LPDDR4.
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**********************************************************************
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*/
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#ifndef LPDDR4_IF_H
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#define LPDDR4_IF_H
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#include <linux/types.h>
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/** @defgroup ConfigInfo Configuration and Hardware Operation Information
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* The following definitions specify the driver operation environment that
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* is defined by hardware configuration or client code. These defines are
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* located in the header file of the core driver.
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* @{
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*/
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/**********************************************************************
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* Defines
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**********************************************************************/
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/** Number of chip-selects */
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#define LPDDR4_MAX_CS (2U)
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/** Number of accessible registers for controller. */
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#define LPDDR4_CTL_REG_COUNT (459U)
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/** Number of accessible registers for PHY Independent Module. */
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#define LPDDR4_PHY_INDEP_REG_COUNT (300U)
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/** Number of accessible registers for PHY. */
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#define LPDDR4_PHY_REG_COUNT (1423U)
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/**
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* @}
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*/
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/** @defgroup DataStructure Dynamic Data Structures
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* This section defines the data structures used by the driver to provide
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* hardware information, modification and dynamic operation of the driver.
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* These data structures are defined in the header file of the core driver
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* and utilized by the API.
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* @{
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*/
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/**********************************************************************
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* Forward declarations
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**********************************************************************/
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typedef struct lpddr4_config_s lpddr4_config;
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typedef struct lpddr4_privatedata_s lpddr4_privatedata;
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typedef struct lpddr4_debuginfo_s lpddr4_debuginfo;
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typedef struct lpddr4_fspmoderegs_s lpddr4_fspmoderegs;
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typedef struct lpddr4_reginitdata_s lpddr4_reginitdata;
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/**********************************************************************
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* Enumerations
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**********************************************************************/
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/** This is used to indicate whether the Controller, PHY, or PHY Independent module is addressed. */
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typedef enum
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{
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LPDDR4_CTL_REGS = 0U,
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LPDDR4_PHY_REGS = 1U,
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LPDDR4_PHY_INDEP_REGS = 2U
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} lpddr4_regblock;
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/** Controller status or error interrupts. */
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typedef enum
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{
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LPDDR4_RESET_DONE = 0U,
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LPDDR4_BUS_ACCESS_ERROR = 1U,
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LPDDR4_MULTIPLE_BUS_ACCESS_ERROR = 2U,
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LPDDR4_ECC_MULTIPLE_CORR_ERROR = 3U,
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LPDDR4_ECC_MULTIPLE_UNCORR_ERROR = 4U,
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LPDDR4_ECC_WRITEBACK_EXEC_ERROR = 5U,
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LPDDR4_ECC_SCRUB_DONE = 6U,
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LPDDR4_ECC_SCRUB_ERROR = 7U,
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LPDDR4_PORT_COMMAND_ERROR = 8U,
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LPDDR4_MC_INIT_DONE = 9U,
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LPDDR4_LP_DONE = 10U,
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LPDDR4_BIST_DONE = 11U,
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LPDDR4_WRAP_ERROR = 12U,
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LPDDR4_INVALID_BURST_ERROR = 13U,
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LPDDR4_RDLVL_ERROR = 14U,
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LPDDR4_RDLVL_GATE_ERROR = 15U,
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LPDDR4_WRLVL_ERROR = 16U,
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LPDDR4_CA_TRAINING_ERROR = 17U,
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LPDDR4_DFI_UPDATE_ERROR = 18U,
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LPDDR4_MRR_ERROR = 19U,
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LPDDR4_PHY_MASTER_ERROR = 20U,
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LPDDR4_WRLVL_REQ = 21U,
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LPDDR4_RDLVL_REQ = 22U,
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LPDDR4_RDLVL_GATE_REQ = 23U,
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LPDDR4_CA_TRAINING_REQ = 24U,
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LPDDR4_LEVELING_DONE = 25U,
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LPDDR4_PHY_ERROR = 26U,
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LPDDR4_MR_READ_DONE = 27U,
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LPDDR4_TEMP_CHANGE = 28U,
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LPDDR4_TEMP_ALERT = 29U,
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LPDDR4_SW_DQS_COMPLETE = 30U,
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LPDDR4_DQS_OSC_BV_UPDATED = 31U,
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LPDDR4_DQS_OSC_OVERFLOW = 32U,
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LPDDR4_DQS_OSC_VAR_OUT = 33U,
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LPDDR4_MR_WRITE_DONE = 34U,
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LPDDR4_INHIBIT_DRAM_DONE = 35U,
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LPDDR4_DFI_INIT_STATE = 36U,
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LPDDR4_DLL_RESYNC_DONE = 37U,
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LPDDR4_TDFI_TO = 38U,
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LPDDR4_DFS_DONE = 39U,
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LPDDR4_DFS_STATUS = 40U,
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LPDDR4_REFRESH_STATUS = 41U,
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LPDDR4_ZQ_STATUS = 42U,
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LPDDR4_SW_REQ_MODE = 43U,
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LPDDR4_LOR_BITS = 44U
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} lpddr4_ctlinterrupt;
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/** PHY Independent Module status or error interrupts. */
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typedef enum
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{
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LPDDR4_PHY_INDEP_INIT_DONE_BIT = 0U,
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LPDDR4_PHY_INDEP_CONTROL_ERROR_BIT = 1U,
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LPDDR4_PHY_INDEP_CA_PARITY_ERR_BIT = 2U,
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LPDDR4_PHY_INDEP_RDLVL_ERROR_BIT = 3U,
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LPDDR4_PHY_INDEP_RDLVL_GATE_ERROR_BIT = 4U,
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LPDDR4_PHY_INDEP_WRLVL_ERROR_BIT = 5U,
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LPDDR4_PHY_INDEP_CALVL_ERROR_BIT = 6U,
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LPDDR4_PHY_INDEP_WDQLVL_ERROR_BIT = 7U,
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LPDDR4_PHY_INDEP_UPDATE_ERROR_BIT = 8U,
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LPDDR4_PHY_INDEP_RDLVL_REQ_BIT = 9U,
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LPDDR4_PHY_INDEP_RDLVL_GATE_REQ_BIT = 10U,
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LPDDR4_PHY_INDEP_WRLVL_REQ_BIT = 11U,
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LPDDR4_PHY_INDEP_CALVL_REQ_BIT = 12U,
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LPDDR4_PHY_INDEP_WDQLVL_REQ_BIT = 13U,
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LPDDR4_PHY_INDEP_LVL_DONE_BIT = 14U,
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LPDDR4_PHY_INDEP_BIST_DONE_BIT = 15U,
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LPDDR4_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 16U,
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LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U
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} lpddr4_phyindepinterrupt;
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/** List of informations and warnings from driver. */
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typedef enum
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{
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LPDDR4_DRV_NONE = 0U,
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LPDDR4_DRV_SOC_PLL_UPDATE = 1U
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} lpddr4_infotype;
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/** Low power interface wake up timing parameters */
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typedef enum
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{
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LPDDR4_LPI_PD_WAKEUP_FN = 0U,
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LPDDR4_LPI_SR_SHORT_WAKEUP_FN = 1U,
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LPDDR4_LPI_SR_LONG_WAKEUP_FN = 2U,
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LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN = 3U,
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LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN = 4U,
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LPDDR4_LPI_SRPD_LONG_WAKEUP_FN = 5U,
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LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN = 6U
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} lpddr4_lpiwakeupparam;
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/** Half Datapath mode setting */
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typedef enum
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{
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LPDDR4_REDUC_ON = 0U,
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LPDDR4_REDUC_OFF = 1U
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} lpddr4_reducmode;
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/** ECC Control parameter setting */
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typedef enum
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{
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LPDDR4_ECC_DISABLED = 0U,
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LPDDR4_ECC_ENABLED = 1U,
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LPDDR4_ECC_ERR_DETECT = 2U,
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LPDDR4_ECC_ERR_DETECT_CORRECT = 3U
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} lpddr4_eccenable;
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/** Data Byte Inversion mode setting */
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typedef enum
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{
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LPDDR4_DBI_RD_ON = 0U,
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LPDDR4_DBI_RD_OFF = 1U,
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LPDDR4_DBI_WR_ON = 2U,
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LPDDR4_DBI_WR_OFF = 3U
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} lpddr4_dbimode;
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/** Controller Frequency Set Point number */
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typedef enum
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{
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LPDDR4_FSP_0 = 0U,
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LPDDR4_FSP_1 = 1U,
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LPDDR4_FSP_2 = 2U
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} lpddr4_ctlfspnum;
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/**********************************************************************
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* Callbacks
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**********************************************************************/
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/**
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* Reports informations and warnings that need to be communicated.
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* Params:
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* pD - driver state info specific to this instance.
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* infoType - Type of information.
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*/
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typedef void (*lpddr4_infocallback)(const lpddr4_privatedata* pd, lpddr4_infotype infotype);
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/**
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* Reports interrupts received by the controller.
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* Params:
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* pD - driver state info specific to this instance.
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* ctlInterrupt - Interrupt raised
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* chipSelect - Chip for which interrupt raised
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*/
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typedef void (*lpddr4_ctlcallback)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt ctlinterrupt, uint8_t chipselect);
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/**
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* Reports interrupts received by the PHY Independent Module.
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* Params:
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* privateData - driver state info specific to this instance.
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* phyIndepInterrupt - Interrupt raised
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* chipSelect - Chip for which interrupt raised
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*/
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typedef void (*lpddr4_phyindepcallback)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt phyindepinterrupt, uint8_t chipselect);
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/**
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* @}
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*/
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/** @defgroup DriverFunctionAPI Driver Function API
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* Prototypes for the driver API functions. The user application can link statically to the
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* necessary API functions and call them directly.
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* @{
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*/
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/**********************************************************************
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* API methods
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**********************************************************************/
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/**
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* Checks configuration object.
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* @param[in] config Driver/hardware configuration required.
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* @param[out] configSize Size of memory allocations required.
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* @return CDN_EOK on success (requirements structure filled).
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* @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints.
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*/
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uint32_t lpddr4_probe(const lpddr4_config* config, uint16_t* configsize);
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/**
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* Init function to be called after LPDDR4_probe() to set up the
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* driver configuration. Memory should be allocated for drv_data
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* (using the size determined using LPDDR4_probe) before calling this
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* API. init_settings should be initialised with base addresses for
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* PHY Indepenent Module, Controller and PHY before calling this
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* function. If callbacks are required for interrupt handling, these
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* should also be configured in init_settings.
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* @param[in] pD Driver state info specific to this instance.
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* @param[in] cfg Specifies driver/hardware configuration.
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* @return CDN_EOK on success
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* @return EINVAL if illegal/inconsistent values in cfg.
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* @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s) required by 'config' parameters.
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*/
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uint32_t lpddr4_init(lpddr4_privatedata* pd, const lpddr4_config* cfg);
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/**
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* Start the driver.
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* @param[in] pD Driver state info specific to this instance.
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*/
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uint32_t lpddr4_start(const lpddr4_privatedata* pd);
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/**
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* Read a register from the controller, PHY or PHY Independent Module
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* @param[in] pD Driver state info specific to this instance.
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* @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
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* @param[in] regOffset Register offset
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* @param[out] regValue Register value read
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* @return CDN_EOK on success.
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* @return EINVAL if regOffset if out of range or regValue is NULL
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*/
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uint32_t lpddr4_readreg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t* regvalue);
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/**
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* Write a register in the controller, PHY or PHY Independent Module
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* @param[in] pD Driver state info specific to this instance.
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* @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
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* @param[in] regOffset Register offset
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* @param[in] regValue Register value to be written
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* @return CDN_EOK on success.
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* @return EINVAL if regOffset is out of range or regValue is NULL
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*/
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uint32_t lpddr4_writereg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t regvalue);
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/**
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* Read a memory mode register from DRAM
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* @param[in] pD Driver state info specific to this instance.
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* @param[in] readModeRegVal Value to set in 'read_modereg' parameter.
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* @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices.
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* @param[out] mmrStatus Status of mode register read(mrr) instruction.
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* @return CDN_EOK on success.
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* @return EINVAL if regNumber is out of range or regValue is NULL
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*/
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uint32_t lpddr4_getmmrregister(const lpddr4_privatedata* pd, uint32_t readmoderegval, uint64_t* mmrvalue, uint8_t* mmrstatus);
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/**
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* Write a memory mode register in DRAM
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* @param[in] pD Driver state info specific to this instance.
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* @param[in] writeModeRegVal Value to set in 'write_modereg' parameter.
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* @param[out] mrwStatus Status of mode register write(mrw) instruction.
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* @return CDN_EOK on success.
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* @return EINVAL if regNumber is out of range or regValue is NULL
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*/
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uint32_t lpddr4_setmmrregister(const lpddr4_privatedata* pd, uint32_t writemoderegval, uint8_t* mrwstatus);
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/**
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* Write a set of initialisation values to the controller registers
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* @param[in] pD Driver state info specific to this instance.
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* @param[in] regValues Register values to be written
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* @return CDN_EOK on success.
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* @return EINVAL if regValues is NULL
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*/
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uint32_t lpddr4_writectlconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
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/**
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* Write a set of initialisation values to the PHY registers
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* @param[in] pD Driver state info specific to this instance.
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* @param[in] regValues Register values to be written
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* @return CDN_EOK on success.
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* @return EINVAL if regValues is NULL
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*/
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uint32_t lpddr4_writephyconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
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/**
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* Write a set of initialisation values to the PHY Independent Module
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* registers
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* @param[in] pD Driver state info specific to this instance.
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* @param[in] regValues Register values to be written
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* @return CDN_EOK on success.
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* @return EINVAL if regValues is NULL
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*/
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uint32_t lpddr4_writephyindepconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
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/**
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* Read values of the controller registers in bulk (Set 'updateCtlReg'
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* to read) and store in memory.
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* @param[in] pD Driver state info specific to this instance.
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* @param[out] regValues Register values which are read
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* @return CDN_EOK on success.
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* @return EINVAL if regValues is NULL
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*/
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uint32_t lpddr4_readctlconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
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/**
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* Read the values of the PHY module registers in bulk (Set
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* 'updatePhyReg' to read) and store in memory.
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* @param[in] pD Driver state info specific to this instance.
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* @param[out] regValues Register values which are read
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* @return CDN_EOK on success.
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* @return EINVAL if regValues is NULL
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*/
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uint32_t lpddr4_readphyconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
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/**
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* Read the values of the PHY Independent module registers in bulk(Set
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* 'updatePhyIndepReg' to read) and store in memory.
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* @param[in] pD Driver state info specific to this instance.
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* @param[out] regValues Register values which are read
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* @return CDN_EOK on success.
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* @return EINVAL if regValues is NULL
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*/
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uint32_t lpddr4_readphyindepconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
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/**
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* Read the current interrupt mask for the controller
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* @param[in] pD Driver state info specific to this instance.
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* @param[out] mask Value of interrupt mask
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* @return CDN_EOK on success.
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* @return EINVAL if mask pointer is NULL
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*/
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uint32_t lpddr4_getctlinterruptmask(const lpddr4_privatedata* pd, uint64_t* mask);
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/**
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* Sets the interrupt mask for the controller
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* @param[in] pD Driver state info specific to this instance.
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* @param[in] mask Value of interrupt mask to be written
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* @return CDN_EOK on success.
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* @return EINVAL if mask pointer is NULL
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*/
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uint32_t lpddr4_setctlinterruptmask(const lpddr4_privatedata* pd, const uint64_t* mask);
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/**
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* Check whether a specific controller interrupt is active
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* @param[in] pD Driver state info specific to this instance.
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* @param[in] intr Interrupt to be checked
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* @param[out] irqStatus Status of the interrupt, TRUE if active
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* @return CDN_EOK on success.
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* @return EINVAL if intr is not valid
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*/
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uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr, bool* irqstatus);
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/**
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* Acknowledge a specific controller interrupt
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* @param[in] pD Driver state info specific to this instance.
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* @param[in] intr Interrupt to be acknowledged
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* @return CDN_EOK on success.
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* @return EINVAL if intr is not valid
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*/
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uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr);
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/**
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* Read the current interrupt mask for the PHY Independent Module
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* @param[in] pD Driver state info specific to this instance.
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* @param[out] mask Value of interrupt mask
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* @return CDN_EOK on success.
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* @return EINVAL if mask pointer is NULL
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*/
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uint32_t lpddr4_getphyindepinterruptmask(const lpddr4_privatedata* pd, uint32_t* mask);
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/**
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* Sets the interrupt mask for the PHY Independent Module
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* @param[in] pD Driver state info specific to this instance.
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* @param[in] mask Value of interrupt mask to be written
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* @return CDN_EOK on success.
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* @return EINVAL if mask pointer is NULL
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*/
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uint32_t lpddr4_setphyindepinterruptmask(const lpddr4_privatedata* pd, const uint32_t* mask);
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/**
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* Check whether a specific PHY Independent Module interrupt is active
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* @param[in] pD Driver state info specific to this instance.
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* @param[in] intr Interrupt to be checked
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* @param[out] irqStatus Status of the interrupt, TRUE if active
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* @return CDN_EOK on success.
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* @return EINVAL if intr is not valid
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*/
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uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr, bool* irqstatus);
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/**
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* Acknowledge a specific PHY Independent Module interrupt
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* @param[in] pD Driver state info specific to this instance.
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* @param[in] intr Interrupt to be acknowledged
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* @return CDN_EOK on success.
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* @return EINVAL if intr is not valid
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*/
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uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr);
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/**
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* Retrieve status information after a failed init. The
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* DebugStructInfo will be filled in with error codes which can be
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|
* referenced against the driver documentation for further details.
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* @param[in] pD Driver state info specific to this instance.
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* @param[out] debugInfo status
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* @return CDN_EOK on success.
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* @return EINVAL if debugInfo is NULL
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*/
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uint32_t lpddr4_getdebuginitinfo(const lpddr4_privatedata* pd, lpddr4_debuginfo* debuginfo);
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/**
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* Get the current value of Low power Interface wake up time.
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* @param[in] pD Driver state info specific to this instance.
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* @param[in] lpiWakeUpParam LPI timing parameter
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* @param[in] fspNum Frequency copy
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* @param[out] cycles Timing value(in cycles)
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* @return CDN_EOK on success.
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* @return EINVAL if powerMode is NULL
|
|
*/
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uint32_t lpddr4_getlpiwakeuptime(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
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/**
|
|
* Set the current value of Low power Interface wake up time.
|
|
* @param[in] pD Driver state info specific to this instance.
|
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* @param[in] lpiWakeUpParam LPI timing parameter
|
|
* @param[in] fspNum Frequency copy
|
|
* @param[in] cycles Timing value(in cycles)
|
|
* @return CDN_EOK on success.
|
|
* @return EINVAL if powerMode is NULL
|
|
*/
|
|
uint32_t lpddr4_setlpiwakeuptime(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
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|
|
/**
|
|
* Get the current value for ECC auto correction
|
|
* @param[in] pD Driver state info specific to this instance.
|
|
* @param[out] eccParam ECC parameter setting
|
|
* @return CDN_EOK on success.
|
|
* @return EINVAL if on_off is NULL
|
|
*/
|
|
uint32_t lpddr4_geteccenable(const lpddr4_privatedata* pd, lpddr4_eccenable* eccparam);
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|
|
/**
|
|
* Set the value for ECC auto correction. This API must be called
|
|
* before startup of memory.
|
|
* @param[in] pD Driver state info specific to this instance.
|
|
* @param[in] eccParam ECC control parameter setting
|
|
* @return CDN_EOK on success.
|
|
* @return EINVAL if on_off is NULL
|
|
*/
|
|
uint32_t lpddr4_seteccenable(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam);
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|
|
/**
|
|
* Get the current value for the Half Datapath option
|
|
* @param[in] pD Driver state info specific to this instance.
|
|
* @param[out] mode Half Datapath setting
|
|
* @return CDN_EOK on success.
|
|
* @return EINVAL if mode is NULL
|
|
*/
|
|
uint32_t lpddr4_getreducmode(const lpddr4_privatedata* pd, lpddr4_reducmode* mode);
|
|
|
|
/**
|
|
* Set the value for the Half Datapath option. This API must be
|
|
* called before startup of memory.
|
|
* @param[in] pD Driver state info specific to this instance.
|
|
* @param[in] mode Half Datapath setting
|
|
* @return CDN_EOK on success.
|
|
* @return EINVAL if mode is NULL
|
|
*/
|
|
uint32_t lpddr4_setreducmode(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode);
|
|
|
|
/**
|
|
* Get the current value for Data Bus Inversion setting. This will be
|
|
* compared with the current DRAM setting using the MR3 register.
|
|
* @param[in] pD Driver state info specific to this instance.
|
|
* @param[out] on_off DBI read value
|
|
* @return CDN_EOK on success.
|
|
* @return EINVAL if on_off is NULL
|
|
*/
|
|
uint32_t lpddr4_getdbireadmode(const lpddr4_privatedata* pd, bool* on_off);
|
|
|
|
/**
|
|
* Get the current value for Data Bus Inversion setting. This will be
|
|
* compared with the current DRAM setting using the MR3 register.
|
|
* @param[in] pD Driver state info specific to this instance.
|
|
* @param[out] on_off DBI write value
|
|
* @return CDN_EOK on success.
|
|
* @return EINVAL if on_off is NULL
|
|
*/
|
|
uint32_t lpddr4_getdbiwritemode(const lpddr4_privatedata* pd, bool* on_off);
|
|
|
|
/**
|
|
* Set the mode for Data Bus Inversion. This will also be set in DRAM
|
|
* using the MR3 controller register. This API must be called before
|
|
* startup of memory.
|
|
* @param[in] pD Driver state info specific to this instance.
|
|
* @param[in] mode status
|
|
* @return CDN_EOK on success.
|
|
* @return EINVAL if mode is NULL
|
|
*/
|
|
uint32_t lpddr4_setdbimode(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode);
|
|
|
|
/**
|
|
* Get the current value for the refresh rate (reading Refresh per
|
|
* command timing).
|
|
* @param[in] pD Driver state info specific to this instance.
|
|
* @param[in] fspNum Frequency set number
|
|
* @param[out] cycles Refresh rate (in cycles)
|
|
* @return CDN_EOK on success.
|
|
* @return EINVAL if rate is NULL
|
|
*/
|
|
uint32_t lpddr4_getrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
|
|
|
|
/**
|
|
* Set the refresh rate (writing Refresh per command timing).
|
|
* @param[in] pD Driver state info specific to this instance.
|
|
* @param[in] fspNum Frequency set number
|
|
* @param[in] cycles Refresh rate (in cycles)
|
|
* @return CDN_EOK on success.
|
|
* @return EINVAL if rate is NULL
|
|
*/
|
|
uint32_t lpddr4_setrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
|
|
|
|
/**
|
|
* Handle Refreshing per chip select
|
|
* @param[in] pD Driver state info specific to this instance.
|
|
* @param[in] trefInterval status
|
|
* @return CDN_EOK on success.
|
|
* @return EINVAL if chipSelect is invalid
|
|
*/
|
|
uint32_t lpddr4_refreshperchipselect(const lpddr4_privatedata* pd, const uint32_t trefinterval);
|
|
|
|
#endif /* LPDDR4_IF_H */
|