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3bb3f266ee
The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
120 lines
3.9 KiB
C
120 lines
3.9 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/******************************************************************************
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*
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* Copyright (C) 2017-2018 Cadence Design Systems, Inc.
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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*
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* cps_drv_lpddr4.h
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* Interface for the Register Accaess Layer of Cadence Platform Service (CPS)
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*****************************************************************************
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*/
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#ifndef CPS_DRV_H_
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#define CPS_DRV_H_
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#include <stddef.h>
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#include <inttypes.h>
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#include <asm/io.h>
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/**
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* \brief Read a 32-bit value from memory.
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* \param reg address of the memory mapped hardware register
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* \return the value at the given address
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*/
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#define CPS_REG_READ(reg) (readl((volatile uint32_t*)(reg)))
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/**
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* \brief Write a 32-bit address value to memory.
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* \param reg address of the memory mapped hardware register
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* \param value unsigned 32-bit value to write
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*/
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#define CPS_REG_WRITE(reg, value) (writel((uint32_t)(value), (volatile uint32_t*)(reg)))
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/**
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* \brief Subtitue the value of fld macro and concatinate with required string
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* \param fld field name
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*/
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#define CPS_FLD_MASK(fld) (fld ## _MASK)
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#define CPS_FLD_SHIFT(fld) (fld ## _SHIFT)
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#define CPS_FLD_WIDTH(fld) (fld ## _WIDTH)
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#define CPS_FLD_WOCLR(fld) (fld ## _WOCLR)
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#define CPS_FLD_WOSET(fld) (fld ## _WOSET)
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/**
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* \brief Read a value of bit-field from the register value.
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* \param reg register name
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* \param fld field name
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* \param reg_value register value
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* \return bit-field value
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*/
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#define CPS_FLD_READ(fld, reg_value) (cps_fldread((uint32_t)(CPS_FLD_MASK(fld)), \
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(uint32_t)(CPS_FLD_SHIFT(fld)), \
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(uint32_t)(reg_value)))
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/**
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* \brief Write a value of the bit-field into the register value.
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* \param reg register name
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* \param fld field name
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* \param reg_value register value
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* \param value value to be written to bit-field
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* \return modified register value
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*/
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#define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((uint32_t)(CPS_FLD_MASK(fld)), \
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(uint32_t)(CPS_FLD_SHIFT(fld)), \
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(uint32_t)(reg_value), (uint32_t)(value)))
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/**
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* \brief Set bit within the register value.
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* \param reg register name
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* \param fld field name
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* \param reg_value register value
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* \return modified register value
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*/
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#define CPS_FLD_SET(fld, reg_value) (cps_fldset((uint32_t)(CPS_FLD_WIDTH(fld)), \
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(uint32_t)(CPS_FLD_MASK(fld)), \
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(uint32_t)(CPS_FLD_WOCLR(fld)), \
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(uint32_t)(reg_value)))
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static inline uint32_t cps_fldread(uint32_t mask, uint32_t shift, uint32_t reg_value)
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{
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uint32_t result = (reg_value & mask) >> shift;
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return (result);
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}
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/**
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* \brief Write a value of the bit-field into the register value.
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* \param mask mask for the bit-field
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* \param shift bit-field shift from LSB
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* \param reg_value register value
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* \param value value to be written to bit-field
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* \return modified register value
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*/
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static inline uint32_t cps_fldwrite(uint32_t mask, uint32_t shift, uint32_t reg_value, uint32_t value)
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{
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uint32_t new_value = (value << shift) & mask;
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new_value = (reg_value & ~mask) | new_value;
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return (new_value);
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}
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/**
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* \brief Set bit within the register value.
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* \param width width of the bit-field
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* \param mask mask for the bit-field
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* \param is_woclr is bit-field has 'write one to clear' flag set
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* \param reg_value register value
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* \return modified register value
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*/
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static inline uint32_t cps_fldset(uint32_t width, uint32_t mask, uint32_t is_woclr, uint32_t reg_value)
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{
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uint32_t new_value = reg_value;
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/* Confirm the field to be bit and not write to clear type */
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if ((width == 1U) && (is_woclr == 0U)) {
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new_value |= mask;
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}
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return (new_value);
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}
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#endif /* CPS_DRV_H_ */
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