York Sun 61bd2f75f5 drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3 ... Freescale LSCH3 platforms use two DDR controlers interleaving mode out of reset. It can be configured to disable one controller. To support this operation, the driver needs to detect and skip the disabled controller. Signed-off-by: York Sun <yorksun@freescale.com>		2015-11-30 09:11:11 -08:00
..
arm_ddr_gen3.c	driver/ddr/fsl: Add support for multiple DDR clocks	2015-02-24 13:09:18 -08:00
ctrl_regs.c	drivers/ddr/fsl_ddr: Make SR_IE configurable	2015-10-30 09:19:41 -07:00
ddr1_dimm_params.c	driver/ddr/fsl: Add support for multiple DDR clocks	2015-02-24 13:09:18 -08:00
ddr2_dimm_params.c	driver/ddr/fsl: Add support for multiple DDR clocks	2015-02-24 13:09:18 -08:00
ddr3_dimm_params.c	driver/ddr/fsl: Add support for multiple DDR clocks	2015-02-24 13:09:18 -08:00
ddr4_dimm_params.c	driver/ddr/fsl: Fix driver to support empty first slot	2015-04-23 08:55:53 -07:00
fsl_ddr_gen4.c	armv8: ls2085a: Add support of LS2085A SoC	2015-11-30 09:10:47 -08:00
interactive.c	driver/ddr/fsl: Fix driver to support empty first slot	2015-04-23 08:55:53 -07:00
lc_common_dimm_params.c	driver/ddr/fsl: Fix driver to support empty first slot	2015-04-23 08:55:53 -07:00
main.c	drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3	2015-11-30 09:11:11 -08:00
Makefile	Various Makefiles: Add SPDX-License-Identifier tags	2015-11-10 09:19:52 -05:00
mpc85xx_ddr_gen1.c	Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx	2013-11-25 11:43:46 -08:00
mpc85xx_ddr_gen2.c	Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx	2013-11-25 11:43:46 -08:00
mpc85xx_ddr_gen3.c	driver/ddr/fsl: Add support for multiple DDR clocks	2015-02-24 13:09:18 -08:00
mpc86xx_ddr.c	Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx	2013-11-25 11:43:46 -08:00
options.c	drivers/ddr/fsl: Adjust bstopre value	2015-08-03 12:06:38 -07:00
util.c	drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3	2015-11-30 09:11:11 -08:00