York Sun 61bd2f75f5 drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3 ... Freescale LSCH3 platforms use two DDR controlers interleaving mode out of reset. It can be configured to disable one controller. To support this operation, the driver needs to detect and skip the disabled controller. Signed-off-by: York Sun <yorksun@freescale.com>		2015-11-30 09:11:11 -08:00
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altera	ddr: altera: Repair uninited variable	2015-08-23 11:56:19 +02:00
fsl	drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3	2015-11-30 09:11:11 -08:00
marvell	arm: mvebu: Fix SAR1_CPU_CORE_MASK	2015-11-17 23:41:41 +01:00