u-boot-brain/drivers/clk/altera
Chee Hong Ang 32d630fc1d clk: socfpga: Read the clock parent's register base in probe function
This commit (82de42fa14) calls child's
ofdata_to_platdata() method before the parent is probed in dm core.
This has caused the driver no longer able to get the correct parent
clock's register base in the ofdata_to_platdata() method because the
parent clocks will only be probed after the child's ofdata_to_platdata().
To resolve this, the clock parent's register base will only be retrieved
by the child in probe() method instead of ofdata_to_platdata().

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-04-05 19:07:13 -04:00
..
clk-agilex.c clk: agilex: Add clock driver for Agilex 2020-01-07 14:38:33 +01:00
clk-agilex.h clk: agilex: Add clock driver for Agilex 2020-01-07 14:38:33 +01:00
clk-arria10.c clk: socfpga: Read the clock parent's register base in probe function 2020-04-05 19:07:13 -04:00
Makefile clk: agilex: Add clock driver for Agilex 2020-01-07 14:38:33 +01:00