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https://github.com/brain-hackers/u-boot-brain
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087bfe67ac
Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
28 lines
518 B
C
28 lines
518 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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* Copyright 2019 NXP Semiconductors
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*
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*/
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#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
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#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
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#include <common.h>
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enum mxc_clock {
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MXC_ARM_CLK = 0,
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MXC_BUS_CLK,
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MXC_UART_CLK,
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MXC_ESDHC_CLK,
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MXC_ESDHC2_CLK,
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MXC_I2C_CLK,
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MXC_DSPI_CLK,
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};
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unsigned int mxc_get_clock(enum mxc_clock clk);
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ulong get_ddr_freq(ulong);
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uint get_svr(void);
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#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */
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