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armv8: fsl-lsch3: add clock support for the second eSDHC

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Layerscape began to use two eSDHC controllers, for example,
LS1028A. They are same IP block with same reference clock.
This patch is to add clock support for the second eSDHC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Yangbo Lu 2019-05-23 11:05:45 +08:00 committed by Prabhakar Kushwaha
parent d17eb57dcf
commit 087bfe67ac
2 changed files with 4 additions and 0 deletions
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2
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
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@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014-2015, Freescale Semiconductor, Inc.
* Copyright 2019 NXP Semiconductors
*
* Derived from arch/power/cpu/mpc85xx/speed.c
*/
@ -214,6 +215,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return get_i2c_freq(0);
#if defined(CONFIG_FSL_ESDHC)
case MXC_ESDHC_CLK:
case MXC_ESDHC2_CLK:
return get_sdhc_freq(0);
#endif
case MXC_DSPI_CLK:

2
arch/arm/include/asm/arch-fsl-layerscape/clock.h
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@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2015 Freescale Semiconductor, Inc.
* Copyright 2019 NXP Semiconductors
*
*/
@ -14,6 +15,7 @@ enum mxc_clock {
MXC_BUS_CLK,
MXC_UART_CLK,
MXC_ESDHC_CLK,
MXC_ESDHC2_CLK,
MXC_I2C_CLK,
MXC_DSPI_CLK,
};