Fabio Estevam 89cfd0f575 mx6: clock: Fix the calculation of PLL_ENET frequency ... According to the mx6 quad reference manual, the DIV_SELECT field of register CCM_ANALOG_PLL_ENETn has the following meaning: "Controls the frequency of the ethernet reference clock. - 00 - 25MHz - 01 - 50MHz - 10 - 100MHz - 11 - 125MHz" Current logic does not handle the 25MHz case correctly, so fix it. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>		2013-12-17 18:38:42 +01:00
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clock.c	mx6: clock: Fix the calculation of PLL_ENET frequency	2013-12-17 18:38:42 +01:00
hab.c	imx: add status reporting for HAB status	2013-08-31 15:06:29 +02:00
Makefile	armv7: convert makefiles to Kbuild style	2013-10-31 12:53:39 -04:00
soc.c	i.MX6: Set and clear the gating bits for Phase Fractional Dividers	2013-08-31 18:09:37 +02:00