Fabio Estevam 89cfd0f575 mx6: clock: Fix the calculation of PLL_ENET frequency ... According to the mx6 quad reference manual, the DIV_SELECT field of register CCM_ANALOG_PLL_ENETn has the following meaning: "Controls the frequency of the ethernet reference clock. - 00 - 25MHz - 01 - 50MHz - 10 - 100MHz - 11 - 125MHz" Current logic does not handle the 25MHz case correctly, so fix it. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>		2013-12-17 18:38:42 +01:00
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cpu	mx6: clock: Fix the calculation of PLL_ENET frequency	2013-12-17 18:38:42 +01:00
dts	exynos5: dts: Add device node for XHCI	2013-10-20 23:42:38 +02:00
imx-common	nitrogen6x: Move setup_sata to common part	2013-12-17 18:12:14 +01:00
include/asm	nitrogen6x: Move setup_sata to common part	2013-12-17 18:12:14 +01:00
lib	cosmetic: remove empty lines at the top of file	2013-11-08 09:41:37 -05:00
config.mk	Coding Style cleanup: replace leading SPACEs by TABs	2013-10-14 16:06:54 -04:00