mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 00:48:52 +09:00
7afc45ad7d
There is a small ordering issue in the master core in that we need to make sure the disabling of the timebase in the SoC is visible before we set the value to 0. We can simply just read back the value to synchronizatize the write, before we set TB to 0. Reported-by: Dan Hettena Tested-by: Dan Hettena Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
||
|---|---|---|
| .. | ||
| 74xx_7xx | ||
| mpc5xx | ||
| mpc5xxx | ||
| mpc8xx | ||
| mpc8xxx | ||
| mpc83xx | ||
| mpc85xx | ||
| mpc86xx | ||
| mpc512x | ||
| mpc824x | ||
| mpc8220 | ||
| mpc8260 | ||
| ppc4xx | ||