mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 18:56:15 +09:00
4baa0ab67d
This patch adds support for initialising & maintaining L2 caches on MIPS systems. The L2 cache configuration may be advertised through either coprocessor 0 or the MIPS Coherence Manager depending upon the system, and support for both is included. If the L2 can be bypassed then we bypass it early in boot & initialise the L1 caches first, such that we can start making use of the L1 instruction cache as early as possible. Otherwise we initialise the L2 first such that the L1s have no opportunity to generate access to the uninitialised L2. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
38 lines
771 B
C
38 lines
771 B
C
/*
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* (C) Copyright 2002-2010
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_GBL_DATA_H
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#define __ASM_GBL_DATA_H
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#include <asm/regdef.h>
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/* Architecture-specific global data */
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struct arch_global_data {
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#ifdef CONFIG_DYNAMIC_IO_PORT_BASE
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unsigned long io_port_base;
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#endif
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#ifdef CONFIG_ARCH_ATH79
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unsigned long id;
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unsigned long soc;
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unsigned long rev;
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unsigned long ver;
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#endif
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#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
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unsigned short l1i_line_size;
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unsigned short l1d_line_size;
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#endif
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#ifdef CONFIG_MIPS_L2_CACHE
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unsigned short l2_line_size;
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#endif
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};
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#include <asm-generic/global_data.h>
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#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0")
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#endif /* __ASM_GBL_DATA_H */
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