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https://github.com/brain-hackers/u-boot-brain
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13539ba705
Add common DPTF (Intel Dynamic Performance and Thermal Framework) files, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
187 lines
2.7 KiB
Plaintext
187 lines
2.7 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2016 Intel Corporation.
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*/
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External (\_PR.CP00._PSS, PkgObj)
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External (\_PR.CP00._TSS, PkgObj)
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External (\_PR.CP00._TPC, MethodObj)
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External (\_PR.CP00._PTC, PkgObj)
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External (\_PR.CP00._TSD, PkgObj)
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External (\_SB.MPDL, IntObj)
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Device (DPTF_CPU_DEVICE)
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{
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Name(_ADR, DPTF_CPU_ADDR)
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Method (_STA)
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{
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If (LEqual (\DPTE, One)) {
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Return (0xF)
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} Else {
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Return (0x0)
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}
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}
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/*
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* Processor Throttling Controls
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*/
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Method (_TSS)
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{
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If (CondRefOf (\_PR.CP00._TSS)) {
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Return (\_PR.CP00._TSS)
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} Else {
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Return (Package ()
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{
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Package () { 0, 0, 0, 0, 0 }
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})
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}
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}
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Method (_TPC)
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{
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If (CondRefOf (\_PR.CP00._TPC)) {
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Return (\_PR.CP00._TPC)
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} Else {
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Return (0)
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}
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}
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Method (_PTC)
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{
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If (CondRefOf (\_PR.CP00._PTC)) {
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Return (\_PR.CP00._PTC)
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} Else {
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Return (Package ()
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{
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Buffer () { 0 },
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Buffer () { 0 }
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})
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}
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}
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Method (_TSD)
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{
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If (CondRefOf (\_PR.CP00._TSD)) {
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Return (\_PR.CP00._TSD)
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} Else {
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Return (Package ()
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{
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Package () { 5, 0, 0, 0, 0 }
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})
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}
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}
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Method (_TDL)
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{
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If (CondRefOf (\_PR.CP00._TSS)) {
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Store (SizeOf (\_PR.CP00._TSS), Local0)
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Decrement (Local0)
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Return (Local0)
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} Else {
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Return (0)
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}
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}
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/*
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* Processor Performance Control
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*/
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Method (_PPC)
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{
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Return (0)
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}
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Method (SPPC, 1)
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{
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Store (Arg0, \PPCM)
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/* Notify OS to re-read _PPC limit on each CPU */
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\PPCN ()
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}
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Method (_PSS)
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{
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If (CondRefOf (\_PR.CP00._PSS)) {
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Return (\_PR.CP00._PSS)
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} Else {
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Return (Package ()
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{
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Package () { 0, 0, 0, 0, 0, 0 }
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})
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}
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}
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Method (_PDL)
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{
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/* Check for mainboard specific _PDL override */
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If (CondRefOf (\_SB.MPDL)) {
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Return (\_SB.MPDL)
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} ElseIf (CondRefOf (\_PR.CP00._PSS)) {
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Store (SizeOf (\_PR.CP00._PSS), Local0)
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Decrement (Local0)
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Return (Local0)
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} Else {
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Return (0)
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}
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}
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/* Return PPCC table defined by mainboard */
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Method (PPCC)
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{
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Return (\_SB.MPPC)
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}
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#ifdef DPTF_CPU_CRITICAL
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Method (_CRT)
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{
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Return (\_SB.DPTF.CTOK (DPTF_CPU_CRITICAL))
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}
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#endif
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#ifdef DPTF_CPU_PASSIVE
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Method (_PSV)
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{
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Return (\_SB.DPTF.CTOK (DPTF_CPU_PASSIVE))
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}
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#endif
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#ifdef DPTF_CPU_ACTIVE_AC0
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Method (_AC0)
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{
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Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC0))
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}
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#endif
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#ifdef DPTF_CPU_ACTIVE_AC1
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Method (_AC1)
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{
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Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC1))
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}
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#endif
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#ifdef DPTF_CPU_ACTIVE_AC2
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Method (_AC2)
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{
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Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC2))
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}
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#endif
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#ifdef DPTF_CPU_ACTIVE_AC3
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Method (_AC3)
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{
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Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC3))
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}
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#endif
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#ifdef DPTF_CPU_ACTIVE_AC4
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Method (_AC4)
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{
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Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC4))
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}
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#endif
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}
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