mirror of
https://github.com/brain-hackers/u-boot-brain
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862e2e75e8
RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to match this convention. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
66 lines
1.2 KiB
ArmAsm
66 lines
1.2 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) 2018 Alexander Graf <agraf@suse.de>
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#ifdef CONFIG_ARCH_RV64I
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#define STORE_IDX(reg, idx) sd reg, (idx*8)(a0)
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#define LOAD_IDX(reg, idx) ld reg, (idx*8)(a0)
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#else
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#define STORE_IDX(reg, idx) sw reg, (idx*4)(a0)
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#define LOAD_IDX(reg, idx) lw reg, (idx*4)(a0)
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#endif
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.pushsection .text.setjmp, "ax"
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ENTRY(setjmp)
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/* Preserve all callee-saved registers and the SP */
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STORE_IDX(s0, 0)
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STORE_IDX(s1, 1)
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STORE_IDX(s2, 2)
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STORE_IDX(s3, 3)
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STORE_IDX(s4, 4)
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STORE_IDX(s5, 5)
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STORE_IDX(s6, 6)
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STORE_IDX(s7, 7)
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STORE_IDX(s8, 8)
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STORE_IDX(s9, 9)
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STORE_IDX(s10, 10)
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STORE_IDX(s11, 11)
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STORE_IDX(ra, 12)
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STORE_IDX(sp, 13)
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li a0, 0
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ret
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ENDPROC(setjmp)
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.popsection
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.pushsection .text.longjmp, "ax"
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ENTRY(longjmp)
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LOAD_IDX(s0, 0)
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LOAD_IDX(s1, 1)
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LOAD_IDX(s2, 2)
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LOAD_IDX(s3, 3)
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LOAD_IDX(s4, 4)
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LOAD_IDX(s5, 5)
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LOAD_IDX(s6, 6)
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LOAD_IDX(s7, 7)
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LOAD_IDX(s8, 8)
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LOAD_IDX(s9, 9)
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LOAD_IDX(s10, 10)
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LOAD_IDX(s11, 11)
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LOAD_IDX(ra, 12)
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LOAD_IDX(sp, 13)
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/* Move the return value in place, but return 1 if passed 0. */
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beq a1, zero, longjmp_1
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mv a0, a1
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ret
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longjmp_1:
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li a0, 1
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ret
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ENDPROC(longjmp)
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.popsection
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