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https://github.com/brain-hackers/u-boot-brain
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1b846fc24d
The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN voltage domain containing the next-generation C711 CPU core. The subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of L2 configurable SRAM/Cache. This subsystem has a CMMU but is not used currently. The inter-processor communication between the main A72 cores and the C711 processor is achieved through shared memory and a Mailbox. Add the DT node for this DSP processor sub-system in the common k3-j721e-main.dtsi file. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
76 lines
1.3 KiB
Plaintext
76 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-j721e-som-p0.dtsi"
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
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};
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aliases {
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remoteproc0 = &mcu_r5fss0_core0;
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remoteproc1 = &mcu_r5fss0_core1;
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remoteproc2 = &main_r5fss0_core0;
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remoteproc3 = &main_r5fss0_core1;
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remoteproc4 = &main_r5fss1_core0;
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remoteproc5 = &main_r5fss1_core1;
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remoteproc6 = &c66_0;
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remoteproc7 = &c66_1;
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remoteproc8 = &c71_0;
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};
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};
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&wkup_uart0 {
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/* Wakeup UART is used by System firmware */
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status = "disabled";
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};
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&main_uart3 {
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/* UART not brought out */
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status = "disabled";
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};
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&main_uart5 {
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/* UART not brought out */
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status = "disabled";
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};
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&main_uart6 {
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/* UART not brought out */
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status = "disabled";
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};
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&main_uart7 {
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/* UART not brought out */
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status = "disabled";
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};
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&main_uart8 {
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/* UART not brought out */
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status = "disabled";
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};
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&main_uart9 {
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/* UART not brought out */
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status = "disabled";
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};
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&main_sdhci0 {
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/* eMMC */
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voltage-ranges = <1800 1800>;
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non-removable;
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ti,driver-strength-ohm = <50>;
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};
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&main_sdhci1 {
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/* SD/MMC */
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voltage-ranges = <1800 1800 3300 3300>;
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ti,driver-strength-ohm = <50>;
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};
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