Ye.Li 4aa7ac30a7 iMX6: Disable the L2 before chaning the PL310 latency ... The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. And setting these registers must have PL310 NOT enabled. But when using Plugin mode boot, the PL310 is enabled by bootrom. The patch disables the PL310 before applying this setting. Signed-off-by: Ye.Li <Ye.Li@freescale.com>		2014-09-09 16:30:40 +02:00
..
clock.c	mx6: add clock enabling functions	2014-09-09 15:32:32 +02:00
ddr.c	arm: mx6: ddr: fix cs0_end calculation	2014-09-09 15:35:00 +02:00
hab.c	imx: correct HAB status for new chip TO	2014-06-17 17:45:09 +02:00
Makefile	mx6: add support of multi-processor command	2014-08-20 11:52:54 +02:00
mp.c	mx6: add support of multi-processor command	2014-08-20 11:52:54 +02:00
soc.c	iMX6: Disable the L2 before chaning the PL310 latency	2014-09-09 16:30:40 +02:00