mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-07 03:50:41 +09:00
48255f5276
Mode pins can be used as output for reset. Xilinx boards are using this feature as additional way how to reset USB phys and also others chips on the boards. Mode1 is used on all these boards for this feature. Let SPL toggle reset on this pin by default. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
142 lines
2.8 KiB
C
142 lines
2.8 KiB
C
/*
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* Copyright 2015 - 2016 Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/spl.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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void board_init_f(ulong dummy)
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{
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psu_init();
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board_early_init_r();
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#ifdef CONFIG_DEBUG_UART
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/* Uart debug for sure */
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debug_uart_init();
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puts("Debug uart enabled\n"); /* or printch() */
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#endif
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/* Delay is required for clocks to be propagated */
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udelay(1000000);
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/* Clear the BSS */
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memset(__bss_start, 0, __bss_end - __bss_start);
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/* No need to call timer init - it is empty for ZynqMP */
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board_init_r(NULL, 0);
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}
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static void ps_mode_reset(ulong mode)
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{
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writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
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mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
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&crlapb_base->boot_pin_ctrl);
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udelay(1);
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writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
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&crlapb_base->boot_pin_ctrl);
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udelay(5);
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writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
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mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
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&crlapb_base->boot_pin_ctrl);
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}
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/*
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* Set default PS_MODE1 which is used for USB ULPI phy reset
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* Also other resets can be connected to this certain pin
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*/
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#ifndef MODE_RESET
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# define MODE_RESET PS_MODE1
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#endif
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#ifdef CONFIG_SPL_BOARD_INIT
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void spl_board_init(void)
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{
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preloader_console_init();
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ps_mode_reset(MODE_RESET);
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board_init();
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}
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#endif
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u32 spl_boot_device(void)
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{
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u32 reg = 0;
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u8 bootmode;
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#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
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/* Change default boot mode at run-time */
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writel(BOOT_MODE_USE_ALT |
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CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
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&crlapb_base->boot_mode);
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#endif
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reg = readl(&crlapb_base->boot_mode);
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bootmode = reg & BOOT_MODES_MASK;
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switch (bootmode) {
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case JTAG_MODE:
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return BOOT_DEVICE_RAM;
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#ifdef CONFIG_SPL_MMC_SUPPORT
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case EMMC_MODE:
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case SD_MODE:
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case SD_MODE1:
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return BOOT_DEVICE_MMC1;
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#endif
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#ifdef CONFIG_SPL_DFU_SUPPORT
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case USB_MODE:
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return BOOT_DEVICE_DFU;
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#endif
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default:
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printf("Invalid Boot Mode:0x%x\n", bootmode);
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break;
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}
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return 0;
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}
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u32 spl_boot_mode(const u32 boot_device)
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{
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switch (spl_boot_device()) {
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case BOOT_DEVICE_RAM:
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return 0;
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case BOOT_DEVICE_MMC1:
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return MMCSD_MODE_FS;
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default:
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puts("spl: error: unsupported device\n");
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hang();
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}
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}
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__weak void psu_init(void)
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{
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/*
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* This function is overridden by the one in
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* board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
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*/
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}
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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