mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
2d48caa47d
The topic-miami SoMs contain a Zynq xc7z015 or xc7z030 SoC, 1GB DDR3L RAM, 32MB QSPI NOR flash and 256MB NAND flash. The topic-miamiplus SoMs contain a Zynq xc7z035, xc7z045 or xc7z100 SoC, 2x 1GB DDR3L RAM, 64MB dual-parallel QSPI flash, clock sources and a fan controller. The "Florida" carrier boards add SD, USB, ethernet and other interfaces. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
35 lines
1.0 KiB
C
35 lines
1.0 KiB
C
/*
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* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
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* (c) Copyright 2016 Topic Embedded Products.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#define OPCODE_EXIT 0U
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#define OPCODE_MASKWRITE 0U
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#define OPCODE_MASKPOLL 1U
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#define OPCODE_MASKDELAY 2U
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#define OPCODE_ADDRESS_MASK (~3U)
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/* Sentinel */
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#define EMIT_EXIT() OPCODE_EXIT
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/* Opcode is in lower 2 bits of address, address is always 4-byte aligned */
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#define EMIT_MASKWRITE(addr, mask, val) OPCODE_MASKWRITE | addr, mask, val
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#define EMIT_MASKPOLL(addr, mask) OPCODE_MASKPOLL | addr, mask
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#define EMIT_MASKDELAY(addr, mask) OPCODE_MASKDELAY | addr, mask
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/* Returns codes of ps7_init* */
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#define PS7_INIT_SUCCESS (0)
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#define PS7_INIT_CORRUPT (1)
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#define PS7_INIT_TIMEOUT (2)
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#define PS7_POLL_FAILED_DDR_INIT (3)
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#define PS7_POLL_FAILED_DMA (4)
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#define PS7_POLL_FAILED_PLL (5)
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/* Called by spl.c */
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int ps7_init(void);
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int ps7_post_config(void);
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/* Defined in ps7_init_common.c */
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int ps7_config(unsigned long *ps7_config_init);
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