ARM: zynq: Add support for the topic-miami system-on-modules and carrier boards
The topic-miami SoMs contain a Zynq xc7z015 or xc7z030 SoC, 1GB DDR3L RAM, 32MB QSPI NOR flash and 256MB NAND flash. The topic-miamiplus SoMs contain a Zynq xc7z035, xc7z045 or xc7z100 SoC, 2x 1GB DDR3L RAM, 64MB dual-parallel QSPI flash, clock sources and a fan controller. The "Florida" carrier boards add SD, USB, ethernet and other interfaces. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Mike Looijmans
Michal Simek
parent
ba4ccf9348
commit
2d48caa47d
|
|
@ -97,6 +97,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
|
|||
zynq-zybo.dtb \
|
||||
zynq-microzed.dtb \
|
||||
zynq-picozed.dtb \
|
||||
zynq-topic-miami.dtb \
|
||||
zynq-topic-miamiplus.dtb \
|
||||
zynq-zc770-xm010.dtb \
|
||||
zynq-zc770-xm011.dtb \
|
||||
zynq-zc770-xm012.dtb \
|
||||
|
|
|
|||
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* Topic Miami board DTS
|
||||
*
|
||||
* Copyright (C) 2014-2016 Topic Embedded Products
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "zynq-7000.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Topic Miami Zynq Board";
|
||||
compatible = "topic,miami", "xlnx,zynq-7000";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem0;
|
||||
serial0 = &uart0;
|
||||
spi0 = &qspi;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhci0;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
is-dual = <0>;
|
||||
num-cs = <1>;
|
||||
flash@0 {
|
||||
compatible = "st,m25p80", "n25q256a";
|
||||
m25p,fast-read;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <100000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@qspi-u-boot-spl {
|
||||
label = "qspi-u-boot-spl";
|
||||
reg = <0x00000 0x10000>;
|
||||
};
|
||||
partition@qspi-u-boot-img {
|
||||
label = "qspi-u-boot-img";
|
||||
reg = <0x10000 0x60000>;
|
||||
};
|
||||
partition@qspi-device-tree {
|
||||
label = "qspi-device-tree";
|
||||
reg = <0x70000 0x10000>;
|
||||
};
|
||||
partition@qspi-linux {
|
||||
label = "qspi-linux";
|
||||
reg = <0x80000 0x400000>;
|
||||
};
|
||||
partition@qspi-rootfs {
|
||||
label = "qspi-rootfs";
|
||||
reg = <0x480000 0x1b80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&clkc {
|
||||
ps-clk-frequency = <33333333>;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Topic Miami Plus board DTS
|
||||
*
|
||||
* Copyright (C) 2016 Topic Embedded Products
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include "zynq-topic-miami.dts"
|
||||
|
||||
/ {
|
||||
model = "Topic Miami+ Zynq Board";
|
||||
compatible = "topic,miamiplus", "xlnx,zynq-7000";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
is-dual = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
TOPIC BOARD
|
||||
M: Mike Looijmans <mike.looijmans@topic.nl>
|
||||
S: Maintained
|
||||
F: board/topic/zynq/
|
||||
F: include/configs/topic*.h
|
||||
F: configs/topic_*_defconfig
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := board.o
|
||||
|
||||
# Remove quotes
|
||||
hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
|
||||
|
||||
obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o ps7_init_common.o
|
||||
|
|
@ -0,0 +1 @@
|
|||
#include "../../xilinx/zynq/board.c"
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
|
||||
* (c) Copyright 2016 Topic Embedded Products.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include "ps7_init_gpl.h"
|
||||
#include <asm/io.h>
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
#define APU_FREQ 666666666
|
||||
|
||||
#define PS7_MASK_POLL_TIME 100000000
|
||||
|
||||
/* IO accessors. No memory barriers desired. */
|
||||
static inline void iowrite(unsigned long val, unsigned long addr)
|
||||
{
|
||||
__raw_writel(val, addr);
|
||||
}
|
||||
|
||||
static inline unsigned long ioread(unsigned long addr)
|
||||
{
|
||||
return __raw_readl(addr);
|
||||
}
|
||||
|
||||
/* start timer */
|
||||
static void perf_start_clock(void)
|
||||
{
|
||||
iowrite((1 << 0) | /* Timer Enable */
|
||||
(1 << 3) | /* Auto-increment */
|
||||
(0 << 8), /* Pre-scale */
|
||||
SCU_GLOBAL_TIMER_CONTROL);
|
||||
}
|
||||
|
||||
/* Compute mask for given delay in miliseconds*/
|
||||
static int get_number_of_cycles_for_delay(unsigned int delay)
|
||||
{
|
||||
return (APU_FREQ / (2 * 1000)) * delay;
|
||||
}
|
||||
|
||||
/* stop timer */
|
||||
static void perf_disable_clock(void)
|
||||
{
|
||||
iowrite(0, SCU_GLOBAL_TIMER_CONTROL);
|
||||
}
|
||||
|
||||
/* stop timer and reset timer count regs */
|
||||
static void perf_reset_clock(void)
|
||||
{
|
||||
perf_disable_clock();
|
||||
iowrite(0, SCU_GLOBAL_TIMER_COUNT_L32);
|
||||
iowrite(0, SCU_GLOBAL_TIMER_COUNT_U32);
|
||||
}
|
||||
|
||||
static void perf_reset_and_start_timer(void)
|
||||
{
|
||||
perf_reset_clock();
|
||||
perf_start_clock();
|
||||
}
|
||||
|
||||
int ps7_config(unsigned long *ps7_config_init)
|
||||
{
|
||||
unsigned long *ptr = ps7_config_init;
|
||||
unsigned long opcode;
|
||||
unsigned long addr;
|
||||
unsigned long val;
|
||||
unsigned long mask;
|
||||
unsigned int numargs;
|
||||
int i;
|
||||
int delay;
|
||||
|
||||
for (;;) {
|
||||
opcode = ptr[0];
|
||||
if (opcode == OPCODE_EXIT)
|
||||
return PS7_INIT_SUCCESS;
|
||||
addr = (opcode & OPCODE_ADDRESS_MASK);
|
||||
|
||||
switch (opcode & ~OPCODE_ADDRESS_MASK) {
|
||||
case OPCODE_MASKWRITE:
|
||||
numargs = 3;
|
||||
mask = ptr[1];
|
||||
val = ptr[2];
|
||||
iowrite((ioread(addr) & ~mask) | (val & mask), addr);
|
||||
break;
|
||||
|
||||
case OPCODE_MASKPOLL:
|
||||
numargs = 2;
|
||||
mask = ptr[1];
|
||||
i = 0;
|
||||
while (!(ioread(addr) & mask)) {
|
||||
if (i == PS7_MASK_POLL_TIME)
|
||||
return PS7_INIT_TIMEOUT;
|
||||
i++;
|
||||
}
|
||||
break;
|
||||
|
||||
case OPCODE_MASKDELAY:
|
||||
numargs = 2;
|
||||
mask = ptr[1];
|
||||
delay = get_number_of_cycles_for_delay(mask);
|
||||
perf_reset_and_start_timer();
|
||||
while (ioread(addr) < delay)
|
||||
;
|
||||
break;
|
||||
|
||||
default:
|
||||
return PS7_INIT_CORRUPT;
|
||||
}
|
||||
|
||||
ptr += numargs;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
|
||||
* (c) Copyright 2016 Topic Embedded Products.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_MASKWRITE 0U
|
||||
#define OPCODE_MASKPOLL 1U
|
||||
#define OPCODE_MASKDELAY 2U
|
||||
#define OPCODE_ADDRESS_MASK (~3U)
|
||||
|
||||
/* Sentinel */
|
||||
#define EMIT_EXIT() OPCODE_EXIT
|
||||
/* Opcode is in lower 2 bits of address, address is always 4-byte aligned */
|
||||
#define EMIT_MASKWRITE(addr, mask, val) OPCODE_MASKWRITE | addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr, mask) OPCODE_MASKPOLL | addr, mask
|
||||
#define EMIT_MASKDELAY(addr, mask) OPCODE_MASKDELAY | addr, mask
|
||||
|
||||
/* Returns codes of ps7_init* */
|
||||
#define PS7_INIT_SUCCESS (0)
|
||||
#define PS7_INIT_CORRUPT (1)
|
||||
#define PS7_INIT_TIMEOUT (2)
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3)
|
||||
#define PS7_POLL_FAILED_DMA (4)
|
||||
#define PS7_POLL_FAILED_PLL (5)
|
||||
|
||||
/* Called by spl.c */
|
||||
int ps7_init(void);
|
||||
int ps7_post_config(void);
|
||||
|
||||
/* Defined in ps7_init_common.c */
|
||||
int ps7_config(unsigned long *ps7_config_init);
|
||||
|
|
@ -0,0 +1,227 @@
|
|||
/*
|
||||
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
|
||||
* (c) Copyright 2016 Topic Embedded Products.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include "../ps7_init_gpl.h"
|
||||
|
||||
static unsigned long ps7_pll_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
|
||||
EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000002U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x00113220U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00024000U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000004U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
static unsigned long ps7_clock_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
|
||||
EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
|
||||
EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
|
||||
EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100141U),
|
||||
EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00100141U),
|
||||
EMIT_MASKWRITE(0XF8000148, 0x00003F31U, 0x00000C01U),
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000601U),
|
||||
EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001803U),
|
||||
EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000C03U),
|
||||
EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U),
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U),
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U),
|
||||
EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U),
|
||||
EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U),
|
||||
EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U),
|
||||
EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FC4C4DU),
|
||||
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
static unsigned long ps7_ddr_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
|
||||
EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
|
||||
EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
|
||||
EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
|
||||
EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
|
||||
EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
|
||||
EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E458D2U),
|
||||
EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
|
||||
EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
|
||||
EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
|
||||
EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
|
||||
EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
|
||||
EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
|
||||
EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
|
||||
EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
|
||||
EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
|
||||
EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
|
||||
EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
|
||||
EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
|
||||
EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
|
||||
EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
|
||||
EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
|
||||
EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
|
||||
EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
|
||||
EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
|
||||
EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
|
||||
EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
|
||||
EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
|
||||
EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
|
||||
EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
|
||||
EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
|
||||
EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
|
||||
EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00025010U),
|
||||
EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00026400U),
|
||||
EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00029418U),
|
||||
EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00027820U),
|
||||
EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000090U),
|
||||
EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x00000080U),
|
||||
EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000098U),
|
||||
EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x000000A0U),
|
||||
EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E9U),
|
||||
EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000EEU),
|
||||
EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000FAU),
|
||||
EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000F3U),
|
||||
EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000D0U),
|
||||
EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000C0U),
|
||||
EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000D8U),
|
||||
EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000E0U),
|
||||
EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
|
||||
EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
|
||||
EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
|
||||
EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
|
||||
EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
|
||||
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
|
||||
EMIT_MASKPOLL(0XF8006054, 0x00000007U),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
static unsigned long ps7_mio_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
|
||||
EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
|
||||
EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
|
||||
EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
|
||||
EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
|
||||
EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
|
||||
EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
|
||||
EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000E60U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
|
||||
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
static unsigned long ps7_peripherals_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
|
||||
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
static unsigned long ps7_post_config_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
|
||||
EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
int ps7_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = ps7_config(ps7_mio_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
ret = ps7_config(ps7_pll_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
ret = ps7_config(ps7_clock_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
ret = ps7_config(ps7_ddr_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
ret = ps7_config(ps7_peripherals_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
return PS7_INIT_SUCCESS;
|
||||
}
|
||||
|
||||
int ps7_post_config(void)
|
||||
{
|
||||
return ps7_config(ps7_post_config_3_0);
|
||||
}
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?)
|
||||
0xf8000700 0x1210 // MIO configuration
|
||||
0xf8000704 0x202
|
||||
0xf8000708 0x202
|
||||
0xf800070c 0x202
|
||||
0xf8000710 0x202
|
||||
0xf8000714 0x202
|
||||
0xf8000718 0x202
|
||||
0xf800071c 0x210
|
||||
0xf8000720 0x202
|
||||
0xf8000724 0x1210
|
||||
0xf8000728 0x1210
|
||||
0xf800072c 0x1210
|
||||
0xf8000730 0x1210
|
||||
0xf8000734 0x1210
|
||||
0xf8000738 0x1211
|
||||
0xf800073c 0x1200
|
||||
0xf8000740 0x1210
|
||||
0xf8000744 0x1210
|
||||
0xf8000748 0x1210
|
||||
0xf800074c 0x1210
|
||||
0xf8000750 0x1210
|
||||
0xf8000754 0x1210
|
||||
0xf8000758 0x1210
|
||||
0xf800075c 0x1210
|
||||
0xf8000760 0x1201
|
||||
0xf8000764 0x200
|
||||
0xf8000768 0x12e1
|
||||
0xf800076c 0x2e0
|
||||
0xf8000770 0x304
|
||||
0xf8000774 0x305
|
||||
0xf8000778 0x304
|
||||
0xf800077c 0x305
|
||||
0xf8000780 0x304
|
||||
0xf8000784 0x304
|
||||
0xf8000788 0x304
|
||||
0xf800078c 0x304
|
||||
0xf8000790 0x305
|
||||
0xf8000794 0x304
|
||||
0xf8000798 0x304
|
||||
0xf800079c 0x304
|
||||
0xf80007a0 0x380
|
||||
0xf80007a4 0x380
|
||||
0xf80007a8 0x380
|
||||
0xf80007ac 0x380
|
||||
0xf80007b0 0x380
|
||||
0xf80007b4 0x380
|
||||
0xf80007b8 0x1261
|
||||
0xf80007bc 0x1260
|
||||
0xf80007c0 0x1261
|
||||
0xf80007c4 0x1261
|
||||
0xf80007c8 0x1240
|
||||
0xf80007cc 0x1240
|
||||
0xf80007d0 0x1240
|
||||
0xf80007d4 0x1240
|
||||
0xf8000830 0x180037
|
||||
0xf8000834 0x3a0039
|
||||
0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 (200 MHz)
|
||||
0xE000D000 0x800238C1 // QSPI config - divide-by-2
|
||||
0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay
|
||||
0xE000D0A0 0x82FF04EB // LQSPI_CFG - QIOREAD mode, Numonyx/Micron
|
||||
|
|
@ -0,0 +1,233 @@
|
|||
/*
|
||||
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
|
||||
* (c) Copyright 2016 Topic Embedded Products.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include "../ps7_init_gpl.h"
|
||||
|
||||
static unsigned long ps7_pll_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
|
||||
EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000002U),
|
||||
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x00113220U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00024000U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKPOLL(0XF800010C, 0x00000004U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
static unsigned long ps7_clock_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
|
||||
EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
|
||||
EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
|
||||
EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100141U),
|
||||
EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00100141U),
|
||||
EMIT_MASKWRITE(0XF8000148, 0x00003F31U, 0x00000C01U),
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000601U),
|
||||
EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001803U),
|
||||
EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000C03U),
|
||||
EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U),
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U),
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U),
|
||||
EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U),
|
||||
EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U),
|
||||
EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U),
|
||||
EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FC4C4DU),
|
||||
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
static unsigned long ps7_ddr_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
|
||||
EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
|
||||
EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
|
||||
EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
|
||||
EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
|
||||
EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
|
||||
EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E458D2U),
|
||||
EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
|
||||
EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
|
||||
EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
|
||||
EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
|
||||
EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
|
||||
EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
|
||||
EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
|
||||
EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
|
||||
EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
|
||||
EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
|
||||
EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
|
||||
EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
|
||||
EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
|
||||
EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
|
||||
EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
|
||||
EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
|
||||
EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
|
||||
EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
|
||||
EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
|
||||
EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
|
||||
EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
|
||||
EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
|
||||
EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
|
||||
EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
|
||||
EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
|
||||
EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
|
||||
EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
|
||||
EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00025010U),
|
||||
EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00026400U),
|
||||
EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00029418U),
|
||||
EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00027820U),
|
||||
EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
|
||||
EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000090U),
|
||||
EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x00000080U),
|
||||
EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000098U),
|
||||
EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x000000A0U),
|
||||
EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E9U),
|
||||
EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000EEU),
|
||||
EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000FAU),
|
||||
EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000F3U),
|
||||
EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000D0U),
|
||||
EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000C0U),
|
||||
EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000D8U),
|
||||
EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000E0U),
|
||||
EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
|
||||
EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
|
||||
EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
|
||||
EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
|
||||
EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
|
||||
EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
|
||||
EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
|
||||
EMIT_MASKPOLL(0XF8006054, 0x00000007U),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
static unsigned long ps7_mio_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
|
||||
EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
|
||||
EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
|
||||
EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
|
||||
EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
|
||||
EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
|
||||
EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
|
||||
EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
|
||||
EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000E60U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
|
||||
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
static unsigned long ps7_peripherals_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
|
||||
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
|
||||
EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
|
||||
EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
|
||||
EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
|
||||
EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
|
||||
EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
|
||||
EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
|
||||
EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
|
||||
EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_MASKDELAY(0XF8F00200, 1),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
static unsigned long ps7_post_config_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
|
||||
EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
|
||||
EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
|
||||
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
|
||||
EMIT_EXIT(),
|
||||
};
|
||||
|
||||
int ps7_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = ps7_config(ps7_mio_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
ret = ps7_config(ps7_pll_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
ret = ps7_config(ps7_clock_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
ret = ps7_config(ps7_ddr_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
ret = ps7_config(ps7_peripherals_init_data_3_0);
|
||||
if (ret != PS7_INIT_SUCCESS)
|
||||
return ret;
|
||||
|
||||
return PS7_INIT_SUCCESS;
|
||||
}
|
||||
|
||||
int ps7_post_config(void)
|
||||
{
|
||||
return ps7_config(ps7_post_config_3_0);
|
||||
}
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 (433 MHz)
|
||||
0xf8000700 0x1202 // MIO configuration
|
||||
0xf8000704 0x1202
|
||||
0xf8000708 0x202
|
||||
0xf800070c 0x202
|
||||
0xf8000710 0x202
|
||||
0xf8000714 0x202
|
||||
0xf8000718 0x202
|
||||
0xf800071c 0x200
|
||||
0xf8000720 0x202
|
||||
0xf8000724 0x202
|
||||
0xf8000728 0x202
|
||||
0xf800072c 0x202
|
||||
0xf8000730 0x202
|
||||
0xf8000734 0x202
|
||||
0xf8000738 0x12e1
|
||||
0xf800073c 0x12e0
|
||||
0xf8000740 0x1202
|
||||
0xf8000744 0x1202
|
||||
0xf8000748 0x1202
|
||||
0xf800074c 0x1202
|
||||
0xf8000750 0x1202
|
||||
0xf8000754 0x1202
|
||||
0xf8000758 0x1203
|
||||
0xf800075c 0x1203
|
||||
0xf8000760 0x1203
|
||||
0xf8000764 0x203
|
||||
0xf8000768 0x1203
|
||||
0xf800076c 0x203
|
||||
0xf8000770 0x304
|
||||
0xf8000774 0x305
|
||||
0xf8000778 0x304
|
||||
0xf800077c 0x305
|
||||
0xf8000780 0x304
|
||||
0xf8000784 0x304
|
||||
0xf8000788 0x304
|
||||
0xf800078c 0x304
|
||||
0xf8000790 0x305
|
||||
0xf8000794 0x304
|
||||
0xf8000798 0x304
|
||||
0xf800079c 0x304
|
||||
0xf80007a0 0x380
|
||||
0xf80007a4 0x380
|
||||
0xf80007a8 0x380
|
||||
0xf80007ac 0x380
|
||||
0xf80007b0 0x380
|
||||
0xf80007b4 0x380
|
||||
0xf80007b8 0x1200
|
||||
0xf80007bc 0x1201
|
||||
0xf80007c0 0x1240
|
||||
0xf80007c4 0x1240
|
||||
0xf80007c8 0x1240
|
||||
0xf80007cc 0x1240
|
||||
0xf80007d0 0x1280
|
||||
0xf80007d4 0x1280
|
||||
0xf8000830 0x2f0037
|
||||
0xf8000834 0x3a0039
|
||||
0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6
|
||||
0xE000D000 0x800238C1 // QSPI config - divide-by-2
|
||||
0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay
|
||||
0xE000D0A0 0xE2FF06EB // LQSPI_CFG - Quad read, dual flash
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SYS_VENDOR="topic"
|
||||
CONFIG_SYS_CONFIG_NAME="topic_miami"
|
||||
CONFIG_ARCH_ZYNQ=y
|
||||
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami"
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_SYS_NO_FLASH=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="zynq-uboot> "
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_EMBED=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_ZYNQ_SDHCI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
# CONFIG_NETDEVICES is not set
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_BASE=0xe0000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_ZYNQ_QSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_CI_UDC=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_G_DNL_MANUFACTURER="Xilinx"
|
||||
CONFIG_G_DNL_VENDOR_NUM=0x03fd
|
||||
CONFIG_G_DNL_PRODUCT_NUM=0x0300
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SYS_VENDOR="topic"
|
||||
CONFIG_SYS_CONFIG_NAME="topic_miamiplus"
|
||||
CONFIG_ARCH_ZYNQ=y
|
||||
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus"
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_SYS_NO_FLASH=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="zynq-uboot> "
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_EMBED=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_ZYNQ_SDHCI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
# CONFIG_NETDEVICES is not set
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_BASE=0xe0000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_ZYNQ_QSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_CI_UDC=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_G_DNL_MANUFACTURER="Xilinx"
|
||||
CONFIG_G_DNL_VENDOR_NUM=0x03fd
|
||||
CONFIG_G_DNL_PRODUCT_NUM=0x0300
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
/*
|
||||
* (C) Copyright 2014 Topic Embedded Products
|
||||
*
|
||||
* Configuration for Zynq Evaluation and Development Board - Miami
|
||||
* See zynq-common.h for Zynq common configs
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_TOPIC_MIAMI_H
|
||||
#define __CONFIG_TOPIC_MIAMI_H
|
||||
|
||||
#define CONFIG_ZYNQ_PS_CLK_FREQ 33333333UL
|
||||
|
||||
#define CONFIG_ZYNQ_I2C0
|
||||
#define CONFIG_ZYNQ_I2C1
|
||||
|
||||
/* Speed up boot time by ignoring the environment which we never used */
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
|
||||
#include "zynq-common.h"
|
||||
|
||||
/* Fixup settings */
|
||||
#undef CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_SIZE 0x8000
|
||||
#undef CONFIG_ENV_OFFSET
|
||||
#define CONFIG_ENV_OFFSET 0x80000
|
||||
|
||||
/* SPL settings */
|
||||
#undef CONFIG_SPL_ETH_SUPPORT
|
||||
#undef CONFIG_SYS_SPI_U_BOOT_OFFS
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
|
||||
#undef CONFIG_SPL_MAX_FOOTPRINT
|
||||
#define CONFIG_SPL_MAX_FOOTPRINT CONFIG_SYS_SPI_U_BOOT_OFFS
|
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
|
||||
/* sspi command isn't useful */
|
||||
#undef CONFIG_CMD_SPI
|
||||
|
||||
/* No useful gpio */
|
||||
#undef CONFIG_ZYNQ_GPIO
|
||||
#undef CONFIG_CMD_GPIO
|
||||
|
||||
/* No falcon support */
|
||||
#undef CONFIG_SPL_OS_BOOT
|
||||
#undef CONFIG_SPL_FPGA_SUPPORT
|
||||
|
||||
/* FPGA commands that we don't use */
|
||||
#undef CONFIG_CMD_FPGA_LOADMK
|
||||
#undef CONFIG_CMD_FPGA_LOADP
|
||||
#undef CONFIG_CMD_FPGA_LOADBP
|
||||
#undef CONFIG_CMD_FPGA_LOADFS
|
||||
|
||||
/* Extras */
|
||||
#define CONFIG_CMD_MEMTEST
|
||||
#undef CONFIG_SYS_MEMTEST_START
|
||||
#define CONFIG_SYS_MEMTEST_START 0
|
||||
#undef CONFIG_SYS_MEMTEST_END
|
||||
#define CONFIG_SYS_MEMTEST_END 0x18000000
|
||||
|
||||
/* Faster flash, ours may run at 108 MHz */
|
||||
#undef CONFIG_SF_DEFAULT_SPEED
|
||||
#define CONFIG_SF_DEFAULT_SPEED 108000000
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#undef CONFIG_SF_DUAL_FLASH
|
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
|
||||
#undef CONFIG_SPI_FLASH_WINBOND
|
||||
#undef CONFIG_SPI_FLASH_ISSI
|
||||
|
||||
/* Setup proper boot sequences for Miami boards */
|
||||
|
||||
#if defined(CONFIG_USB)
|
||||
# define EXTRA_ENV_USB \
|
||||
"usbreset=i2c dev 1 && i2c mw 41 1 ff && i2c mw 41 3 fe && "\
|
||||
"i2c mw 41 1 fe && i2c mw 41 1 ff\0" \
|
||||
"usbboot=run usbreset && if usb start; then " \
|
||||
"echo Booting from USB... && " \
|
||||
"if load usb 0 0x1900000 ${bootscript}; then "\
|
||||
"source 0x1900000; fi; " \
|
||||
"load usb 0 ${kernel_addr} ${kernel_image} && " \
|
||||
"load usb 0 ${devicetree_addr} ${devicetree_image} && " \
|
||||
"load usb 0 ${ramdisk_load_address} ${ramdisk_image} && " \
|
||||
"bootm ${kernel_addr} ${ramdisk_load_address} "\
|
||||
"${devicetree_addr}; " \
|
||||
"fi\0"
|
||||
/* Note that addresses here should match the addresses in the env */
|
||||
# undef DFU_ALT_INFO
|
||||
# define DFU_ALT_INFO \
|
||||
"dfu_alt_info=" \
|
||||
"uImage ram 0x2080000 0x500000;" \
|
||||
"devicetree.dtb ram 0x2000000 0x20000;" \
|
||||
"uramdisk.image.gz ram 0x4000000 0x10000000\0" \
|
||||
"dfu_ram=run usbreset && dfu 0 ram 0\0" \
|
||||
"thor_ram=run usbreset && thordown 0 ram 0\0"
|
||||
#else
|
||||
# define EXTRA_ENV_USB
|
||||
#endif
|
||||
|
||||
#undef CONFIG_PREBOOT
|
||||
|
||||
#undef CONFIG_EXTRA_ENV_SETTINGS
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"kernel_image=uImage\0" \
|
||||
"kernel_addr=0x2080000\0" \
|
||||
"ramdisk_image=uramdisk.image.gz\0" \
|
||||
"ramdisk_load_address=0x4000000\0" \
|
||||
"devicetree_image=devicetree.dtb\0" \
|
||||
"devicetree_addr=0x2000000\0" \
|
||||
"bitstream_image=fpga.bin\0" \
|
||||
"bootscript=autorun.scr\0" \
|
||||
"loadbit_addr=0x100000\0" \
|
||||
"loadbootenv_addr=0x2000000\0" \
|
||||
"kernel_size=0x400000\0" \
|
||||
"devicetree_size=0x10000\0" \
|
||||
"boot_size=0xF00000\0" \
|
||||
"fdt_high=0x20000000\0" \
|
||||
"initrd_high=0x20000000\0" \
|
||||
"mmc_loadbit=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \
|
||||
"mmcinfo && " \
|
||||
"load mmc 0 ${loadbit_addr} ${bitstream_image} && " \
|
||||
"fpga load 0 ${loadbit_addr} ${filesize}\0" \
|
||||
"qspiboot=echo Booting from QSPI flash... && " \
|
||||
"sf probe && " \
|
||||
"sf read ${devicetree_addr} 0xA0000 ${devicetree_size} && " \
|
||||
"sf read ${kernel_addr} 0xC0000 ${kernel_size} && " \
|
||||
"bootm ${kernel_addr} - ${devicetree_addr}\0" \
|
||||
"sdboot=if mmcinfo; then " \
|
||||
"setenv bootargs console=ttyPS0,115200 " \
|
||||
"root=/dev/mmcblk0p2 rw rootfstype=ext4 " \
|
||||
"rootwait quiet ; " \
|
||||
"load mmc 0 ${kernel_addr} ${kernel_image}&& " \
|
||||
"load mmc 0 ${devicetree_addr} ${devicetree_image}&& " \
|
||||
"bootm ${kernel_addr} - ${devicetree_addr}; " \
|
||||
"fi\0" \
|
||||
EXTRA_ENV_USB \
|
||||
DFU_ALT_INFO
|
||||
|
||||
#undef CONFIG_BOOTCOMMAND
|
||||
#define CONFIG_BOOTCOMMAND "if mmcinfo; then " \
|
||||
"if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; " \
|
||||
"fi; fi; run $modeboot"
|
||||
#undef CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
/* Further tweaks to reduce image size */
|
||||
#undef CONFIG_CMD_BOOTZ
|
||||
#undef CONFIG_CMD_NET
|
||||
#undef CONFIG_CMD_AES
|
||||
|
||||
#endif /* __CONFIG_TOPIC_MIAMI_H */
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
#include "topic_miami.h"
|
||||
#define CONFIG_SF_DUAL_FLASH
|
||||
Loading…
Reference in New Issue