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https://github.com/brain-hackers/u-boot-brain
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The mmc host controller on the i.mx6q is called usdhc which is redesigned based on the freescale esdhc controller. The usdhc controller is almost compatible with esdhc except it adds one mix register to support debug/SD3.0 and move the low bit 0-6 of XFERTYP register to the mix control reg low bit 0-6. Thus on i.mx6q, we have the following compared with the previous soc: (can refer to RM of chapter 56.3.3) i.mx6q: mix control: bit 31 - bit 7: Added for debug/SD3.0 support bit 6 - bit 0: move in the XFERTYP register bit 6-0 on previous soc XFERTYP register: bit 31 - bit 7: the same as before, bit 6 - bit 0: no-use previous soc mix control: no XFERTYP register: bit 31 - bit 0: xfertype information Signed-off-by: Jason Liu <jason.hui@linaro.org> Cc: Andy Fleming <afleming@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de> |
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| .. | ||
| bios_emulator | ||
| block | ||
| dma | ||
| fpga | ||
| gpio | ||
| hwmon | ||
| i2c | ||
| input | ||
| misc | ||
| mmc | ||
| mtd | ||
| net | ||
| pci | ||
| pcmcia | ||
| power | ||
| qe | ||
| rtc | ||
| serial | ||
| spi | ||
| tpm | ||
| twserial | ||
| usb | ||
| video | ||
| watchdog | ||