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https://github.com/brain-hackers/u-boot-brain
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45b940d6f9
A prerequisite for using virtualization is to be in HYP mode, which requires the CPU to be in non-secure state first. Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine which switches the CPU to non-secure state by setting the NS and associated bits. According to the ARM architecture reference manual this should not be done in SVC mode, so we have to setup a SMC handler for this. We create a new vector table to avoid interference with other boards. The MVBAR register will be programmed later just before the smc call. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
54 lines
1.6 KiB
ArmAsm
54 lines
1.6 KiB
ArmAsm
/*
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* code for switching cores into non-secure state
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*
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* Copyright (c) 2013 Andre Przywara <andre.przywara@linaro.org>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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/* the vector table for secure state */
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_monitor_vectors:
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.word 0 /* reset */
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.word 0 /* undef */
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adr pc, _secure_monitor
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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/*
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* secure monitor handler
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* U-boot calls this "software interrupt" in start.S
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* This is executed on a "smc" instruction, we use a "smc #0" to switch
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* to non-secure state.
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* We use only r0 and r1 here, due to constraints in the caller.
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*/
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.align 5
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_secure_monitor:
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mrc p15, 0, r1, c1, c1, 0 @ read SCR
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bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits
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orr r1, r1, #0x31 @ enable NS, AW, FW bits
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mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set)
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movs pc, lr @ return to non-secure SVC
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