mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
44b5c40be3
Add support for the SAMA5D27-WLSOM1-EK. It's based on the Microchip WireLess SoM which contains the SAMa5D27 LPDDR2 2Gbits SiP. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> [eugen.hristev@microchip.com]: added u-boot specific dtsi and ported to 2019.10 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
81 lines
1.4 KiB
C
81 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <asm/io.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/atmel_pio4.h>
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#include <asm/arch/atmel_mpddrc.h>
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#include <asm/arch/atmel_sdhci.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/sama5d2.h>
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extern void at91_pda_detect(void);
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_DM_VIDEO
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at91_video_show_board_info();
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#endif
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at91_pda_detect();
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return 0;
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}
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#endif
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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static void board_uart0_hw_init(void)
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{
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atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
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atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
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at91_periph_clk_enable(ATMEL_ID_UART0);
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}
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void board_debug_uart_init(void)
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{
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board_uart0_hw_init();
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}
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#endif
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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#ifdef CONFIG_DEBUG_UART
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debug_uart_init();
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#endif
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return 0;
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}
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#endif
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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return 0;
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}
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#endif
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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