brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

board: atmel: add sama5d27_wlsom1_ek board

Browse Source 
Add support for the SAMA5D27-WLSOM1-EK. It's based on the Microchip
WireLess SoM which contains the SAMa5D27 LPDDR2 2Gbits SiP.

Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
[eugen.hristev@microchip.com]: added u-boot specific dtsi and ported to 2019.10
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
This commit is contained in:
Nicolas Ferre 2019-08-08 07:48:26 +00:00 committed by Eugen Hristev
parent 00561e7d24
commit 44b5c40be3
11 changed files with 411 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/dts/Makefile
View File

@ -727,6 +727,9 @@ dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \
at91-sama5d27_som1_ek.dtb
dtb-$(CONFIG_TARGET_SAMA5D27_WLSOM1_EK) += \
at91-sama5d27_wlsom1_ek.dtb
dtb-$(CONFIG_TARGET_SAMA5D2_ICP) += \
at91-sama5d2_icp.dtb

38
arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi Normal file
View File

@ -0,0 +1,38 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sama5d27_wlsom1_ek-u-boot.dts - Device Tree file for SAMA5D27 WLSOM1 EK
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Eugen Hristev <eugen.hristev@microchip.com>
*/
/ {
chosen {
u-boot,dm-pre-reloc;
};
};
&sdmmc0 {
u-boot,dm-pre-reloc;
};
&uart0 {
u-boot,dm-pre-reloc;
};
&sfr {
u-boot,dm-pre-reloc;
};
&pinctrl_sdmmc0_cmd_dat_default {
u-boot,dm-pre-reloc;
};
&pinctrl_sdmmc0_ck_cd_default {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0_default {
u-boot,dm-pre-reloc;
};

84
arch/arm/dts/at91-sama5d27_wlsom1_ek.dts Normal file
View File

@ -0,0 +1,84 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sama5d27_wlsom1_ek.dts - Device Tree file for SAMA5D27 WLSOM1 EK
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
*/
/dts-v1/;
#include "sama5d27_wlsom1.dtsi"
/ {
model = "Microchip SAMA5D27 WLSOM1 EK";
compatible = "microchip,sama5d27-wlsom1-ek", "microchip,sama5d27-wlsom1", "atmel,sama5d2", "atmel,sama5";
chosen {
stdout-path = &uart0;
};
onewire_tm: onewire {
gpios = <&pioA PIN_PC9 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_onewire_tm_default>;
status = "okay";
w1_eeprom: w1_eeprom@0 {
compatible = "maxim,ds24b33";
status = "okay";
};
};
ahb {
sdmmc0: sdio-host@a0000000 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
status = "okay";
};
apb {
macb0: ethernet@f8008000 {
status = "okay";
};
uart0: serial@f801c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
status = "okay";
};
pioA: gpio@fc038000 {
pinctrl {
pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_DAT0>,
<PIN_PA3__SDMMC0_DAT1>,
<PIN_PA4__SDMMC0_DAT2>,
<PIN_PA5__SDMMC0_DAT3>;
bias-disable;
};
pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA11__SDMMC0_VDDSEL>,
<PIN_PA12__SDMMC0_WP>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
};
pinctrl_uart0_default: uart0_default {
pinmux = <PIN_PB26__URXD0>,
<PIN_PB27__UTXD0>;
bias-disable;
};
pinctrl_onewire_tm_default: onewire_tm_default {
pinmux = <PIN_PC9__GPIO>;
bias-pull-up;
};
};
};
};
};
};

56
arch/arm/dts/sama5d27_wlsom1.dtsi Normal file
View File

@ -0,0 +1,56 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
*/
#include "sama5d2.dtsi"
#include "sama5d2-pinfunc.h"
/ {
model = "Microchip SAMA5D27 WLSOM1";
compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d2", "atmel,sama5";
memory {
reg = <0x20000000 0x10000000>;
};
ahb {
apb {
macb0: ethernet@f8008000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
phy-mode = "rmii";
ethernet-phy@0 {
reg = <0x0>;
};
};
pioA: gpio@fc038000 {
pinctrl {
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PB24__GPIO>;
bias-disable;
};
pinctrl_macb0_rmii: macb0_rmii {
pinmux = <PIN_PB14__GTXCK>,
<PIN_PB15__GTXEN>,
<PIN_PB16__GRXDV>,
<PIN_PB17__GRXER>,
<PIN_PB18__GRX0>,
<PIN_PB19__GRX1>,
<PIN_PB20__GTX0>,
<PIN_PB21__GTX1>,
<PIN_PB22__GMDC>,
<PIN_PB23__GMDIO>;
bias-disable;
};
};
};
};
};
};

15
arch/arm/mach-at91/Kconfig
View File

@ -180,6 +180,20 @@ config TARGET_SAMA5D27_SOM1_EK
processor-based SAMA5D2 MPU with up to 1 Gbit DDR2-SDRAM
in a single package.
config TARGET_SAMA5D27_WLSOM1_EK
bool "SAMA5D27 WLSOM1 EK board"
select SAMA5D2
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select CPU_V7A
help
The SAMA5D27 WLSOM1 embeds SAMA5D2 SiP (System in Package),
a 64Mbit QSPI flash with Mac-address, KSZ8081 Phy. A wireless
module providing bluetooth and wifi is also embedded.
The SAMA5D2 SiP integrates the ARM Cortex-A5
processor-based SAMA5D2 MPU with 2 Gbit LPDDR2-SDRAM
in a single package.
config TARGET_SAMA5D2_ICP
bool "SAMA5D2 Industrial Connectivity Platform (ICP)"
select CPU_V7A
@ -292,6 +306,7 @@ source "board/atmel/at91sam9x5ek/Kconfig"
source "board/atmel/sama5d2_ptc_ek/Kconfig"
source "board/atmel/sama5d2_xplained/Kconfig"
source "board/atmel/sama5d27_som1_ek/Kconfig"
source "board/atmel/sama5d27_wlsom1_ek/Kconfig"
source "board/atmel/sama5d2_icp/Kconfig"
source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"

15
board/atmel/sama5d27_wlsom1_ek/Kconfig Normal file
View File

@ -0,0 +1,15 @@
if TARGET_SAMA5D27_WLSOM1_EK
config SYS_BOARD
default "sama5d27_wlsom1_ek"
config SYS_VENDOR
default "atmel"
config SYS_SOC
default "at91"
config SYS_CONFIG_NAME
default "sama5d27_wlsom1_ek"
endif

7
board/atmel/sama5d27_wlsom1_ek/MAINTAINERS Normal file
View File

@ -0,0 +1,7 @@
SAMA5D27 WLSOM1 EK BOARD
M: Nicolas Ferre <nicolas.ferre@microchip.com>
M: Eugen Hristev <eugen.hristev@microchip.com>
S: Maintained
F: board/atmel/sama5d27_wlsom1_ek/
F: include/configs/sama5d27_wlsom1_ek.h
F: configs/sama5d27_wlsom1_ek_mmc_defconfig

7
board/atmel/sama5d27_wlsom1_ek/Makefile Normal file
View File

@ -0,0 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
#
# Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
obj-y += sama5d27_wlsom1_ek.o

80
board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c Normal file
View File

@ -0,0 +1,80 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
*/
#include <common.h>
#include <debug_uart.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/atmel_pio4.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/atmel_sdhci.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sama5d2.h>
extern void at91_pda_detect(void);
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_DM_VIDEO
at91_video_show_board_info();
#endif
at91_pda_detect();
return 0;
}
#endif
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
static void board_uart0_hw_init(void)
{
atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
at91_periph_clk_enable(ATMEL_ID_UART0);
}
void board_debug_uart_init(void)
{
board_uart0_hw_init();
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
#ifdef CONFIG_DEBUG_UART
debug_uart_init();
#endif
return 0;
}
#endif
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
return 0;
}
#endif
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}

72
configs/sama5d27_wlsom1_ek_mmc_defconfig Normal file
View File

@ -0,0 +1,72 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x4000
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xf801c000
CONFIG_DEBUG_UART_CLOCK=82000000
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_FAT=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
CONFIG_AT91_GENERIC_CLK=y
CONFIG_DM_GPIO=y
CONFIG_ATMEL_PIO4=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHY_MICREL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_W1=y
CONFIG_W1_GPIO=y
CONFIG_W1_EEPROM=y
CONFIG_W1_EEPROM_DS24XXX=y
CONFIG_OF_LIBFDT_OVERLAY=y

34
include/configs/sama5d27_wlsom1_ek.h Normal file
View File

@ -0,0 +1,34 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration file for the SAMA5D27 WLSOM1 EK Board.
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "at91-sama5_common.h"
#undef CONFIG_SYS_AT91_MAIN_CLOCK
#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x10000000
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
/* NAND flash */
#undef CONFIG_CMD_NAND
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#endif
#endif