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The Debug Server driver is responsible for loading the Debug server FW on the Service Processor (Cortex-A5 core) on LS2085A like SoCs and then polling for the successful initialization of the same. TOP MEM HIDE is adjusted to ensure the space required by Debug Server FW is accounted for. MC uses the DDR area which is calculated as: MC DDR region start = Top of DDR - area reserved by Debug Server FW Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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| .. | ||
| cpu.c | ||
| cpu.h | ||
| fdt.c | ||
| lowlevel.S | ||
| Makefile | ||
| mp.c | ||
| mp.h | ||
| README | ||
| speed.c | ||
| speed.h | ||
# # Copyright 2014 Freescale Semiconductor # # SPDX-License-Identifier: GPL-2.0+ # Freescale LayerScape with Chassis Generation 3 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, for example LS2085A.