mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-12 07:43:22 +09:00
40e7bcdee7
The code is now fixed to the point where we can safely enable the L1 data cache. Enable the D-Cache and set it as write-alloc. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
45 lines
719 B
C
45 lines
719 B
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/io.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Print Board information
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*/
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int checkboard(void)
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{
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puts("BOARD: Altera SoCFPGA Cyclone5 Board\n");
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return 0;
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}
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/*
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* Initialization function which happen at early stage of c code
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*/
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int board_early_init_f(void)
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{
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return 0;
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}
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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icache_enable();
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dcache_enable();
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/* Address of boot parameters for ATAG (if ATAG is used) */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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