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![Kevin Scholz](/assets/img/avatar_default.png)
The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
373 lines
8.9 KiB
C
373 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Texas Instruments' J721E DDRSS driver
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*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <ram.h>
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#include <asm/io.h>
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#include <power-domain.h>
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#include <wait_bit.h>
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#include "lpddr4_obj_if.h"
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#include "lpddr4_if.h"
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#include "lpddr4_structs_if.h"
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#include "lpddr4_ctl_regs.h"
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#define SRAM_MAX 512
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#define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80
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#define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0
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struct j721e_ddrss_desc {
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struct udevice *dev;
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void __iomem *ddrss_ss_cfg;
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void __iomem *ddrss_ctrl_mmr;
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struct power_domain ddrcfg_pwrdmn;
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struct power_domain ddrdata_pwrdmn;
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struct clk ddr_clk;
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struct clk osc_clk;
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u32 ddr_freq1;
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u32 ddr_freq2;
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u32 ddr_fhs_cnt;
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};
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static LPDDR4_OBJ *driverdt;
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static lpddr4_config config;
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static lpddr4_privatedata pd;
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static struct j721e_ddrss_desc *ddrss;
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#define TH_MACRO_EXP(fld, str) (fld##str)
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#define TH_FLD_MASK(fld) TH_MACRO_EXP(fld, _MASK)
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#define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT)
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#define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH)
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#define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR)
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#define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET)
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#define str(s) #s
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#define xstr(s) str(s)
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#define CTL_SHIFT 11
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#define PHY_SHIFT 11
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#define PI_SHIFT 10
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#define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\
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char *i, *pstr= xstr(REG); offset = 0;\
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for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\
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offset = offset * 10 + (*i - '0'); }\
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} while (0)
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static void j721e_lpddr4_ack_freq_upd_req(void)
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{
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unsigned int req_type, counter;
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debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
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for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
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if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
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CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
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true, 10000, false)) {
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printf("Timeout during frequency handshake\n");
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hang();
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}
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req_type = readl(ddrss->ddrss_ctrl_mmr +
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CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
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debug("%s: received freq change req: req type = %d, req no. = %d \n",
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__func__, req_type, counter);
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if (req_type == 1)
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clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
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else if (req_type == 2)
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clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2);
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else if (req_type == 0)
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/* Put DDR pll in bypass mode */
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clk_set_rate(&ddrss->ddr_clk,
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clk_get_rate(&ddrss->osc_clk));
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else
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printf("%s: Invalid freq request type\n", __func__);
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writel(0x1, ddrss->ddrss_ctrl_mmr +
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CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
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if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
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CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
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false, 10, false)) {
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printf("Timeout during frequency handshake\n");
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hang();
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}
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writel(0x0, ddrss->ddrss_ctrl_mmr +
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CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
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}
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}
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static void j721e_lpddr4_info_handler(const lpddr4_privatedata * pd,
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lpddr4_infotype infotype)
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{
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if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE) {
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j721e_lpddr4_ack_freq_upd_req();
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}
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}
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static int j721e_ddrss_power_on(struct j721e_ddrss_desc *ddrss)
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{
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int ret;
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debug("%s(ddrss=%p)\n", __func__, ddrss);
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ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
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if (ret) {
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dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
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return ret;
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}
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ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
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if (ret) {
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dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int j721e_ddrss_ofdata_to_priv(struct udevice *dev)
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{
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struct j721e_ddrss_desc *ddrss = dev_get_priv(dev);
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phys_addr_t reg;
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int ret;
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debug("%s(dev=%p)\n", __func__, dev);
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reg = dev_read_addr_name(dev, "cfg");
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if (reg == FDT_ADDR_T_NONE) {
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dev_err(dev, "No reg property for DDRSS wrapper logic\n");
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return -EINVAL;
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}
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ddrss->ddrss_ss_cfg = (void *)reg;
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reg = dev_read_addr_name(dev, "ctrl_mmr_lp4");
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if (reg == FDT_ADDR_T_NONE) {
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dev_err(dev, "No reg property for CTRL MMR\n");
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return -EINVAL;
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}
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ddrss->ddrss_ctrl_mmr = (void *)reg;
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ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
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if (ret) {
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dev_err(dev, "power_domain_get() failed: %d\n", ret);
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return ret;
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}
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ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
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if (ret) {
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dev_err(dev, "power_domain_get() failed: %d\n", ret);
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return ret;
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}
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ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk);
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if (ret)
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dev_err(dev, "clk get failed%d\n", ret);
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ret = clk_get_by_index(dev, 1, &ddrss->osc_clk);
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if (ret)
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dev_err(dev, "clk get failed for osc clk %d\n", ret);
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ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
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if (ret)
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dev_err(dev, "ddr freq1 not populated %d\n", ret);
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ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2);
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if (ret)
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dev_err(dev, "ddr freq2 not populated %d\n", ret);
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ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt);
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if (ret)
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dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
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/* Put DDR pll in bypass mode */
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ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
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if (ret)
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dev_err(dev, "ddr clk bypass failed\n");
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return ret;
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}
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void j721e_lpddr4_probe(void)
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{
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uint32_t status = 0U;
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uint16_t configsize = 0U;
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status = driverdt->probe(&config, &configsize);
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if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
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|| (configsize > SRAM_MAX)) {
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printf("LPDDR4_Probe: FAIL\n");
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hang();
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} else {
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debug("LPDDR4_Probe: PASS\n");
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}
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}
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void j721e_lpddr4_init(void)
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{
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uint32_t status = 0U;
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if ((sizeof(pd) != sizeof(lpddr4_privatedata))
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|| (sizeof(pd) > SRAM_MAX)) {
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printf("LPDDR4_Init: FAIL\n");
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hang();
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}
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config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
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config.infohandler = (lpddr4_infocallback) j721e_lpddr4_info_handler;
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status = driverdt->init(&pd, &config);
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if ((status > 0U) ||
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(pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) ||
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(pd.ctlinterrupthandler != config.ctlinterrupthandler) ||
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(pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) {
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printf("LPDDR4_Init: FAIL\n");
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hang();
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} else {
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debug("LPDDR4_Init: PASS\n");
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}
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}
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void populate_data_array_from_dt(lpddr4_reginitdata * reginit_data)
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{
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int ret, i;
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ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data",
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(u32 *) reginit_data->denalictlreg,
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LPDDR4_CTL_REG_COUNT);
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if (ret)
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printf("Error reading ctrl data\n");
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for (i = 0; i < LPDDR4_CTL_REG_COUNT; i++)
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reginit_data->updatectlreg[i] = true;
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ret = dev_read_u32_array(ddrss->dev, "ti,pi-data",
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(u32 *) reginit_data->denaliphyindepreg,
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LPDDR4_PHY_INDEP_REG_COUNT);
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if (ret)
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printf("Error reading PI data\n");
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for (i = 0; i < LPDDR4_PHY_INDEP_REG_COUNT; i++)
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reginit_data->updatephyindepreg[i] = true;
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ret = dev_read_u32_array(ddrss->dev, "ti,phy-data",
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(u32 *) reginit_data->denaliphyreg,
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LPDDR4_PHY_REG_COUNT);
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if (ret)
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printf("Error reading PHY data\n");
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for (i = 0; i < LPDDR4_PHY_REG_COUNT; i++)
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reginit_data->updatephyreg[i] = true;
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}
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void j721e_lpddr4_hardware_reg_init(void)
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{
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uint32_t status = 0U;
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lpddr4_reginitdata reginitdata;
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populate_data_array_from_dt(®initdata);
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status = driverdt->writectlconfig(&pd, ®initdata);
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if (!status) {
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status = driverdt->writephyindepconfig(&pd, ®initdata);
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}
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if (!status) {
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status = driverdt->writephyconfig(&pd, ®initdata);
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}
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if (status) {
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printf(" ERROR: LPDDR4_HardwareRegInit failed!!\n");
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hang();
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}
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return;
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}
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void j721e_lpddr4_start(void)
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{
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uint32_t status = 0U;
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uint32_t regval = 0U;
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uint32_t offset = 0U;
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TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
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status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val);
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if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
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printf("LPDDR4_StartTest: FAIL\n");
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hang();
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}
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status = driverdt->start(&pd);
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if (status > 0U) {
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printf("LPDDR4_StartTest: FAIL\n");
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hang();
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}
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status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val);
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if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
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printf("LPDDR4_Start: FAIL\n");
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hang();
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} else {
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debug("LPDDR4_Start: PASS\n");
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}
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}
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static int j721e_ddrss_probe(struct udevice *dev)
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{
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int ret;
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ddrss = dev_get_priv(dev);
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debug("%s(dev=%p)\n", __func__, dev);
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ret = j721e_ddrss_ofdata_to_priv(dev);
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if (ret)
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return ret;
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ddrss->dev = dev;
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ret = j721e_ddrss_power_on(ddrss);
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if (ret)
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return ret;
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driverdt = lpddr4_getinstance();
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j721e_lpddr4_probe();
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j721e_lpddr4_init();
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j721e_lpddr4_hardware_reg_init();
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j721e_lpddr4_start();
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return ret;
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}
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static int j721e_ddrss_get_info(struct udevice *dev, struct ram_info *info)
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{
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return 0;
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}
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static struct ram_ops j721e_ddrss_ops = {
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.get_info = j721e_ddrss_get_info,
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};
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static const struct udevice_id j721e_ddrss_ids[] = {
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{.compatible = "ti,j721e-ddrss"},
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{}
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};
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U_BOOT_DRIVER(j721e_ddrss) = {
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.name = "j721e_ddrss",
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.id = UCLASS_RAM,
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.of_match = j721e_ddrss_ids,
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.ops = &j721e_ddrss_ops,
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.probe = j721e_ddrss_probe,
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.priv_auto_alloc_size = sizeof(struct j721e_ddrss_desc),
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};
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