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https://github.com/brain-hackers/u-boot-brain
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3b75e98273
The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com>
66 lines
1.6 KiB
C
66 lines
1.6 KiB
C
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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#define SRDS1_MAX_LANES 4
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static u32 serdes1_prtcl_map;
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struct serdes_config {
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u32 protocol;
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u8 lanes[SRDS1_MAX_LANES];
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};
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static const struct serdes_config serdes1_cfg_tbl[] = {
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/* SerDes 1 */
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{1, {PCIE1, PCIE1, PCIE1, PCIE1} },
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{2, {PCIE1, PCIE1, PCIE1, PCIE1} },
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{3, {PCIE1, PCIE1, NONE, NONE} },
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{4, {PCIE1, PCIE1, NONE, NONE} },
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{5, {PCIE1, NONE, NONE, NONE} },
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{6, {PCIE1, NONE, NONE, NONE} },
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{}
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};
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int is_serdes_configured(enum srds_prtcl device)
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{
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return (1 << device) & serdes1_prtcl_map;
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}
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void fsl_serdes_init(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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u32 pordevsr = in_be32(&gur->pordevsr);
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u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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const struct serdes_config *ptr;
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int lane;
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debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
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if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
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printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
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return;
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}
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ptr = &serdes1_cfg_tbl[srds_cfg];
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if (!ptr->protocol)
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return;
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for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = ptr->lanes[lane];
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serdes1_prtcl_map |= (1 << lane_prtcl);
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}
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}
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