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https://github.com/brain-hackers/u-boot-brain
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5690d5c8f8
Add some fixed IO and mmap addresses for use in the device tree and with some early-init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
30 lines
683 B
C
30 lines
683 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2017 Intel Corporation.
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* Take from coreboot project file of the same name
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*/
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#ifndef _ASM_ARCH_IOMAP_H
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#define _ASM_ARCH_IOMAP_H
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#define R_ACPI_PM1_TMR 0x8
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/* Put p2sb at 0xd0000000 in TPL */
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#define IOMAP_P2SB_BAR 0xd0000000
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#define IOMAP_SPI_BASE 0xfe010000
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#define IOMAP_ACPI_BASE 0x400
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#define IOMAP_ACPI_SIZE 0x100
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/*
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* Use UART2. To use UART1 you need to set '2' to '1', change device tree serial
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* node name and 'reg' property, and update CONFIG_DEBUG_UART_BASE.
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*/
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#define PCH_DEV_UART PCI_BDF(0, 0x18, 2)
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#define PCH_DEV_LPC PCI_BDF(0, 0x1f, 0)
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#define PCH_DEV_SPI PCI_BDF(0, 0x0d, 2)
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#endif
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