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7c4f9b3755
When doing DDR scrub, the DDR may enter into self refresh if the selfref_en is enabled before DDR scrub. This will cause scrub can't complete that SBRSTAT.scrub_done won't be set. Since the selfref_en can be programmed during the course of normal operation, move it after DDR scrub Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
253 lines
7.7 KiB
C
253 lines
7.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018-2019 NXP
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*/
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#include <common.h>
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#include <errno.h>
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#include <log.h>
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#include <asm/io.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
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{
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int i = 0;
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for (i = 0; i < num; i++) {
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reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
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ddrc_cfg++;
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}
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}
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#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
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void ddrc_inline_ecc_scrub(unsigned int start_address,
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unsigned int range_address)
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{
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unsigned int tmp;
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/* Step1: Enable quasi-dynamic programming */
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reg32_write(DDRC_SWCTL(0), 0x00000000);
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/* Step2: Set ECCCFG1.ecc_parity_region_lock to 1 */
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reg32setbit(DDRC_ECCCFG1(0), 0x4);
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/* Step3: Block the AXI ports from taking the transaction */
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reg32_write(DDRC_PCTRL_0(0), 0x0);
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/* Step4: Set scrub start address */
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reg32_write(DDRC_SBRSTART0(0), start_address);
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/* Step5: Set scrub range address */
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reg32_write(DDRC_SBRRANGE0(0), range_address);
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/* Step6: Set scrub_mode to write */
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reg32_write(DDRC_SBRCTL(0), 0x00000014);
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/* Step7: Set the desired pattern through SBRWDATA0 registers */
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reg32_write(DDRC_SBRWDATA0(0), 0x55aa55aa);
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/* Step8: Enable the SBR by programming SBRCTL.scrub_en=1 */
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reg32setbit(DDRC_SBRCTL(0), 0x0);
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/* Step9: Poll SBRSTAT.scrub_done=1 */
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tmp = reg32_read(DDRC_SBRSTAT(0));
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while (tmp != 0x00000002)
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tmp = reg32_read(DDRC_SBRSTAT(0)) & 0x2;
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/* Step10: Poll SBRSTAT.scrub_busy=0 */
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tmp = reg32_read(DDRC_SBRSTAT(0));
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while (tmp != 0x0)
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tmp = reg32_read(DDRC_SBRSTAT(0)) & 0x1;
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/* Step11: Disable SBR by programming SBRCTL.scrub_en=0 */
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clrbits_le32(DDRC_SBRCTL(0), 0x1);
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/* Step12: Prepare for normal scrub operation(Read) and set scrub_interval*/
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reg32_write(DDRC_SBRCTL(0), 0x100);
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/* Step13: Enable the SBR by programming SBRCTL.scrub_en=1 */
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reg32_write(DDRC_SBRCTL(0), 0x101);
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/* Step14: Enable AXI ports by programming */
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reg32_write(DDRC_PCTRL_0(0), 0x1);
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/* Step15: Disable quasi-dynamic programming */
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reg32_write(DDRC_SWCTL(0), 0x00000001);
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}
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void ddrc_inline_ecc_scrub_end(unsigned int start_address,
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unsigned int range_address)
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{
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/* Step1: Enable quasi-dynamic programming */
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reg32_write(DDRC_SWCTL(0), 0x00000000);
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/* Step2: Block the AXI ports from taking the transaction */
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reg32_write(DDRC_PCTRL_0(0), 0x0);
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/* Step3: Set scrub start address */
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reg32_write(DDRC_SBRSTART0(0), start_address);
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/* Step4: Set scrub range address */
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reg32_write(DDRC_SBRRANGE0(0), range_address);
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/* Step5: Disable SBR by programming SBRCTL.scrub_en=0 */
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clrbits_le32(DDRC_SBRCTL(0), 0x1);
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/* Step6: Prepare for normal scrub operation(Read) and set scrub_interval */
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reg32_write(DDRC_SBRCTL(0), 0x100);
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/* Step7: Enable the SBR by programming SBRCTL.scrub_en=1 */
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reg32_write(DDRC_SBRCTL(0), 0x101);
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/* Step8: Enable AXI ports by programming */
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reg32_write(DDRC_PCTRL_0(0), 0x1);
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/* Step9: Disable quasi-dynamic programming */
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reg32_write(DDRC_SWCTL(0), 0x00000001);
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}
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#endif
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void __weak board_dram_ecc_scrub(void)
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{
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}
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int ddr_init(struct dram_timing_info *dram_timing)
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{
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unsigned int tmp, initial_drate, target_freq;
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int ret;
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debug("DDRINFO: start DRAM init\n");
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/* Step1: Follow the power up procedure */
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if (is_imx8mq()) {
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reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F);
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
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reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
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} else {
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F);
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
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}
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debug("DDRINFO: cfg clk\n");
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/* change the clock source of dram_apb_clk_root: source 4 800MHz /4 = 200MHz */
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clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) |
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CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
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/* disable iso */
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reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
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reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
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initial_drate = dram_timing->fsp_msg[0].drate;
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/* default to the frequency point 0 clock */
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ddrphy_init_set_dfi_clk(initial_drate);
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/* D-aasert the presetn */
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
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/* Step2: Program the dwc_ddr_umctl2 registers */
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debug("DDRINFO: ddrc config start\n");
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ddr_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
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debug("DDRINFO: ddrc config done\n");
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/* Step3: De-assert reset signal(core_ddrc_rstn & aresetn_n) */
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
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/*
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* Step4: Disable auto-refreshes, self-refresh, powerdown, and
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* assertion of dfi_dram_clk_disable by setting RFSHCTL3.dis_auto_refresh = 1,
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* PWRCTL.powerdown_en = 0, and PWRCTL.selfref_en = 0, PWRCTL.en_dfi_dram_clk_disable = 0
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*/
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reg32_write(DDRC_DBG1(0), 0x00000000);
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reg32_write(DDRC_RFSHCTL3(0), 0x0000001);
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reg32_write(DDRC_PWRCTL(0), 0xa0);
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/* if ddr type is LPDDR4, do it */
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tmp = reg32_read(DDRC_MSTR(0));
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if (tmp & (0x1 << 5) && !is_imx8mn())
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reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */
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/* determine the initial boot frequency */
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target_freq = reg32_read(DDRC_MSTR2(0)) & 0x3;
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target_freq = (tmp & (0x1 << 29)) ? target_freq : 0x0;
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/* Step5: Set SWCT.sw_done to 0 */
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reg32_write(DDRC_SWCTL(0), 0x00000000);
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/* Set the default boot frequency point */
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clrsetbits_le32(DDRC_DFIMISC(0), (0x1f << 8), target_freq << 8);
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/* Step6: Set DFIMISC.dfi_init_complete_en to 0 */
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clrbits_le32(DDRC_DFIMISC(0), 0x1);
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/* Step7: Set SWCTL.sw_done to 1; need to polling SWSTAT.sw_done_ack */
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reg32_write(DDRC_SWCTL(0), 0x00000001);
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do {
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tmp = reg32_read(DDRC_SWSTAT(0));
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} while ((tmp & 0x1) == 0x0);
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/*
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* Step8 ~ Step13: Start PHY initialization and training by
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* accessing relevant PUB registers
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*/
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debug("DDRINFO:ddrphy config start\n");
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ret = ddr_cfg_phy(dram_timing);
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if (ret)
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return ret;
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debug("DDRINFO: ddrphy config done\n");
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/*
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* step14 CalBusy.0 =1, indicates the calibrator is actively
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* calibrating. Wait Calibrating done.
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*/
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do {
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tmp = reg32_read(DDRPHY_CalBusy(0));
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} while ((tmp & 0x1));
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debug("DDRINFO:ddrphy calibration done\n");
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/* Step15: Set SWCTL.sw_done to 0 */
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reg32_write(DDRC_SWCTL(0), 0x00000000);
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/* Apply rank-to-rank workaround */
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update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1);
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/* Step16: Set DFIMISC.dfi_init_start to 1 */
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setbits_le32(DDRC_DFIMISC(0), (0x1 << 5));
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/* Step17: Set SWCTL.sw_done to 1; need to polling SWSTAT.sw_done_ack */
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reg32_write(DDRC_SWCTL(0), 0x00000001);
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do {
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tmp = reg32_read(DDRC_SWSTAT(0));
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} while ((tmp & 0x1) == 0x0);
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/* Step18: Polling DFISTAT.dfi_init_complete = 1 */
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do {
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tmp = reg32_read(DDRC_DFISTAT(0));
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} while ((tmp & 0x1) == 0x0);
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/* Step19: Set SWCTL.sw_done to 0 */
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reg32_write(DDRC_SWCTL(0), 0x00000000);
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/* Step20: Set DFIMISC.dfi_init_start to 0 */
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clrbits_le32(DDRC_DFIMISC(0), (0x1 << 5));
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/* Step21: optional */
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/* Step22: Set DFIMISC.dfi_init_complete_en to 1 */
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setbits_le32(DDRC_DFIMISC(0), 0x1);
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/* Step23: Set PWRCTL.selfref_sw to 0 */
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clrbits_le32(DDRC_PWRCTL(0), (0x1 << 5));
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/* Step24: Set SWCTL.sw_done to 1; need polling SWSTAT.sw_done_ack */
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reg32_write(DDRC_SWCTL(0), 0x00000001);
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do {
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tmp = reg32_read(DDRC_SWSTAT(0));
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} while ((tmp & 0x1) == 0x0);
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/* Step25: Wait for dwc_ddr_umctl2 to move to normal operating mode by monitoring
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* STAT.operating_mode signal */
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do {
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tmp = reg32_read(DDRC_STAT(0));
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} while ((tmp & 0x3) != 0x1);
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/* Step26: Set back register in Step4 to the original values if desired */
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reg32_write(DDRC_RFSHCTL3(0), 0x0000000);
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/* enable port 0 */
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reg32_write(DDRC_PCTRL_0(0), 0x00000001);
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debug("DDRINFO: ddrmix config done\n");
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board_dram_ecc_scrub();
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/* enable selfref_en by default */
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setbits_le32(DDRC_PWRCTL(0), 0x1);
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/* save the dram timing config into memory */
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dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
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return 0;
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}
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