mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
a6ac775bae
MV_DDR_FREQ_SAR lets the DDR frequency be determined by hardware strapping. This also has the side effect of running the DDR clock in synchronous mode with the CPU core clock rather than from an independent PLL. We've seen this improve reliability in operation across a number of boards and temperature ranges. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de> |
||
|---|---|---|
| .. | ||
| common | ||
| SBx81LIFKW | ||
| SBx81LIFXCAT | ||
| x530 | ||