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https://github.com/brain-hackers/u-boot-brain
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372286217f
Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: Paul Burton <paul.burton@imgtec.com> [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
119 lines
2.6 KiB
C
119 lines
2.6 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/cacheops.h>
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#include <asm/mipsregs.h>
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static inline unsigned long icache_line_size(void)
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{
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unsigned long conf1, il;
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if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
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return CONFIG_SYS_ICACHE_LINE_SIZE;
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conf1 = read_c0_config1();
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il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
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if (!il)
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return 0;
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return 2 << il;
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}
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static inline unsigned long dcache_line_size(void)
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{
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unsigned long conf1, dl;
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if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
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return CONFIG_SYS_DCACHE_LINE_SIZE;
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conf1 = read_c0_config1();
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dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
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if (!dl)
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return 0;
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return 2 << dl;
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}
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void flush_cache(ulong start_addr, ulong size)
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{
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unsigned long ilsize = icache_line_size();
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unsigned long dlsize = dcache_line_size();
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const void *addr, *aend;
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/* aend will be miscalculated when size is zero, so we return here */
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if (size == 0)
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return;
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addr = (const void *)(start_addr & ~(dlsize - 1));
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aend = (const void *)((start_addr + size - 1) & ~(dlsize - 1));
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if (ilsize == dlsize) {
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/* flush I-cache & D-cache simultaneously */
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while (1) {
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mips_cache(HIT_WRITEBACK_INV_D, addr);
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mips_cache(HIT_INVALIDATE_I, addr);
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if (addr == aend)
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break;
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addr += dlsize;
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}
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return;
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}
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/* flush D-cache */
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while (1) {
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mips_cache(HIT_WRITEBACK_INV_D, addr);
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if (addr == aend)
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break;
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addr += dlsize;
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}
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/* flush I-cache */
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addr = (const void *)(start_addr & ~(ilsize - 1));
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aend = (const void *)((start_addr + size - 1) & ~(ilsize - 1));
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while (1) {
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mips_cache(HIT_INVALIDATE_I, addr);
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if (addr == aend)
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break;
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addr += ilsize;
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}
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}
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void flush_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = dcache_line_size();
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const void *addr = (const void *)(start_addr & ~(lsize - 1));
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const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
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/* aend will be miscalculated when size is zero, so we return here */
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if (start_addr == stop)
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return;
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while (1) {
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mips_cache(HIT_WRITEBACK_INV_D, addr);
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if (addr == aend)
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break;
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addr += lsize;
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}
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}
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void invalidate_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = dcache_line_size();
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const void *addr = (const void *)(start_addr & ~(lsize - 1));
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const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
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/* aend will be miscalculated when size is zero, so we return here */
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if (start_addr == stop)
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return;
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while (1) {
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mips_cache(HIT_INVALIDATE_D, addr);
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if (addr == aend)
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break;
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addr += lsize;
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}
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}
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