Paul Burton 372286217f MIPS: Split I & D cache line size config ... Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: Paul Burton <paul.burton@imgtec.com> [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>		2016-05-31 09:44:24 +02:00
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cpu	MIPS: provide a default u-boot-spl.lds	2016-05-31 09:38:11 +02:00
dts	malta: Use device model & tree for UART	2016-05-26 01:34:13 +02:00
include/asm	MIPS: Split I & D cache line size config	2016-05-31 09:44:24 +02:00
lib	MIPS: Split I & D cache line size config	2016-05-31 09:44:24 +02:00
mach-ath79	mips: ath79: ar933x: Avoid warning with gcc5	2016-05-26 01:34:14 +02:00
mach-au1x00	MIPS: Kconfig: optimize gcc -march and -mtune setup	2016-01-16 21:06:46 +01:00
mach-pic32	board: Add Microchip PIC32MZ[DA]-Starter-Kit board.	2016-02-01 22:14:01 +01:00
config.mk	MIPS: provide a default u-boot-spl.lds	2016-05-31 09:38:11 +02:00
Kconfig	MIPS: Split I & D cache line size config	2016-05-31 09:44:24 +02:00
Makefile	MIPS: add tune for MIPS 34kc	2016-05-31 09:38:11 +02:00