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36d0a42b68
u-boot-brain/arch/mips/cpu/xburst
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Marek Vasut 36d0a42b68 dm: mips: Fix lb60 WDT control 
Write the TSCR register via 32bit write instead of 16bit one.
The register is 32bit wide and bit 16 is being set, triggering
gcc overflow error and making the code broken.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel <zpxu@ingenic.cn>
Cc: Shinya Kuribayashi <skuribay@pobox.com>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2012-08-17 20:13:48 +02:00
..
config.mk MIPS: Ingenic XBurst Jz4740 processor support 2011-10-10 22:06:12 +09:00
cpu.c dm: mips: Fix lb60 WDT control 2012-08-17 20:13:48 +02:00
jz4740.c MIPS: Ingenic XBurst Jz4740 processor support 2011-10-10 22:06:12 +09:00
jz_serial.c MIPS: Ingenic XBurst Jz4740 processor support 2011-10-10 22:06:12 +09:00
Makefile MIPS: Ingenic XBurst Jz4740 processor support 2011-10-10 22:06:12 +09:00
start.S MIPS: Ingenic XBurst Jz4740 processor support 2011-10-10 22:06:12 +09:00
timer.c MIPS: Ingenic XBurst Jz4740 processor support 2011-10-10 22:06:12 +09:00