Chee Hong Ang 35d847ed90 clk: agilex: Handle clock configuration differently in SPL and U-Boot proper ... Since warm reset may optionally set the CLock Manager to'boot mode', the clock driver should always force the Agilex's Clock Manager to 'boot mode' before the clock driver start configuring the Clock Manager in SPL. In SSBL, clock driver will skip the Clock Manager configuration if it's already being setup by SPL (Clock Manager NOT in 'boot mode') to prevent any inaccurate clocking issues happened on HPS peripherals such as UART, MAC and etc. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>		2020-10-09 17:53:10 +08:00
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clk-agilex.c	clk: agilex: Handle clock configuration differently in SPL and U-Boot proper	2020-10-09 17:53:10 +08:00
clk-agilex.h	common: Drop linux/bitops.h from common header	2020-05-18 21:19:23 -04:00
clk-arria10.c	treewide: convert devfdt_get_addr() to dev_read_addr()	2020-07-25 14:46:57 -06:00
Makefile	clk: agilex: Add clock driver for Agilex	2020-01-07 14:38:33 +01:00