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https://github.com/brain-hackers/u-boot-brain
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ba932bc846
Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach, which is a cheap development platform with RZ/A1H SoC. The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Currently supported are UART, ethernet and RPC SPI. The board can be booted from RPC SPI by writing the u-boot.bin binary to the beginning of the SPI NOR, e.g. using the "sf" command. The board can also be booted via JTAG by setting text base to 0x20020000, loading u-boot.bin there via JTAG and executing it from that address. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
79 lines
1.3 KiB
Plaintext
79 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source extras for U-Boot for the GR Peach board
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*
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* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
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*/
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#include "r7s72100-gr-peach.dts"
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/ {
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aliases {
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spi0 = &rpc;
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};
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soc {
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u-boot,dm-pre-reloc;
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};
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leds {
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led1 {
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label = "peach:bottom:red";
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};
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led-red {
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label = "peach:tri:red";
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gpios = <&port6 13 GPIO_ACTIVE_HIGH>;
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};
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led-green {
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label = "peach:tri:green";
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gpios = <&port6 14 GPIO_ACTIVE_HIGH>;
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};
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led-blue {
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label = "peach:tri:blue";
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gpios = <&port6 15 GPIO_ACTIVE_HIGH>;
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};
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};
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rpc: rpc@0xee200000 {
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compatible = "renesas,rpc-r7s72100", "renesas,rpc";
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reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>;
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bank-width = <2>;
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num-cs = <1>;
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status = "okay";
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spi-max-frequency = <50000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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flash0: spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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reg = <0>;
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status = "okay";
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};
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};
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};
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&ostm0 {
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u-boot,dm-pre-reloc;
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};
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&pinctrl {
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u-boot,dm-pre-reloc;
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};
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&scif2 {
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u-boot,dm-pre-reloc;
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clock = <66666666>; /* ToDo: Replace by DM clock driver */
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};
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&scif2_pins {
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u-boot,dm-pre-reloc;
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};
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