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https://github.com/brain-hackers/u-boot-brain
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![Chris Brandt](/assets/img/avatar_default.png)
Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach, which is a cheap development platform with RZ/A1H SoC. The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Currently supported are UART, ethernet and RPC SPI. The board can be booted from RPC SPI by writing the u-boot.bin binary to the beginning of the SPI NOR, e.g. using the "sf" command. The board can also be booted via JTAG by setting text base to 0x20020000, loading u-boot.bin there via JTAG and executing it from that address. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
54 lines
1.2 KiB
Plaintext
54 lines
1.2 KiB
Plaintext
CONFIG_ARM=y
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# CONFIG_SPL_SYS_THUMB_BUILD is not set
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CONFIG_ARCH_RMOBILE=y
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CONFIG_SYS_TEXT_BASE=0x18000000
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CONFIG_RZA1=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_BOOTDELAY=3
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_HUSH_PARSER=y
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# CONFIG_CMD_ELF is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_SNTP=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_MAC_PARTITION=y
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CONFIG_OF_CONTROL=y
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CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_USE_ENV_SPI_BUS=y
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CONFIG_ENV_SPI_BUS=0
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CONFIG_USE_ENV_SPI_CS=y
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CONFIG_ENV_SPI_CS=0
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CONFIG_USE_ENV_SPI_MAX_HZ=y
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CONFIG_ENV_SPI_MAX_HZ=50000000
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CONFIG_USE_ENV_SPI_MODE=y
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CONFIG_ENV_SPI_MODE=0x0
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_HAVE_BLOCK_DEVICE=y
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CONFIG_DM_GPIO=y
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CONFIG_RZA1_GPIO=y
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CONFIG_LED=y
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CONFIG_LED_GPIO=y
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# CONFIG_MMC is not set
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_MACRONIX=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_DM_ETH=y
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CONFIG_SH_ETHER=y
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CONFIG_PINCTRL=y
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CONFIG_SCIF_CONSOLE=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_RENESAS_RPC_SPI=y
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CONFIG_TIMER=y
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CONFIG_RENESAS_OSTM_TIMER=y
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CONFIG_OF_LIBFDT_OVERLAY=y
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# CONFIG_EFI_LOADER is not set
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