Lukas Auer 31f9058994 riscv: do not blindly modify the mstatus CSR ... The mstatus CSR includes WPRI (writes preserve values, reads ignore values) fields and must therefore not be set to zero without preserving these fields. It is not apparent why mstatus is set to zero here since it is not required for U-Boot to run. Remove it. This instruction and others encode zero as an immediate. RISC-V has the zero register for this purpose. Replace the immediates with the zero register. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>		2018-11-26 13:57:32 +08:00
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ax25	riscv: Move do_reset() to a common place	2018-10-03 17:48:43 +08:00
qemu	riscv: Move do_reset() to a common place	2018-10-03 17:48:43 +08:00
cpu.c	riscv: Add a helper routine to print CPU information	2018-10-03 17:47:55 +08:00
Makefile	riscv: Make start.S available for all targets	2018-10-03 17:48:14 +08:00
start.S	riscv: do not blindly modify the mstatus CSR	2018-11-26 13:57:32 +08:00
u-boot.lds	riscv: Make start.S available for all targets	2018-10-03 17:48:14 +08:00