Lukas Auer 31f9058994 riscv: do not blindly modify the mstatus CSR ... The mstatus CSR includes WPRI (writes preserve values, reads ignore values) fields and must therefore not be set to zero without preserving these fields. It is not apparent why mstatus is set to zero here since it is not required for U-Boot to run. Remove it. This instruction and others encode zero as an immediate. RISC-V has the zero register for this purpose. Replace the immediates with the zero register. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>		2018-11-26 13:57:32 +08:00
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cpu	riscv: do not blindly modify the mstatus CSR	2018-11-26 13:57:32 +08:00
dts	riscv: ae350: Clean up mixed tabs and spaces in the dts	2018-10-03 17:48:19 +08:00
include/asm	riscv: do not reimplement generic io functions	2018-11-26 13:57:30 +08:00
lib	riscv: implement the invalidate_icache_* functions	2018-11-26 13:57:31 +08:00
config.mk	riscv: enable -fdata-sections	2018-11-26 13:57:29 +08:00
Kconfig	riscv: add Kconfig entries for the C and A ISA extensions	2018-11-26 13:57:29 +08:00
Makefile	riscv: set -march and -mabi based on the Kconfig configuration	2018-11-26 13:57:29 +08:00