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https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 03:36:16 +09:00
f588b4d205
Now that we have added driver model support to the TSEC driver, convert ls1021atwr board to use it. This depends on previous DM series for ls1021atwr: http://patchwork.ozlabs.org/patch/561855/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> [Vladimir] Made the following changes: - Added 'status = "disabled";' for all Ethernet ports in ls1021a.dtsi - Fixed the confusion between the SGMII/TBI PCS for enet0 and enet1 - a mistake ported over from Linux. Each SGMII PCS lies on the private MDIO bus of the interface (and the RGMII enet2 has no SGMII PCS). - Added CONFIG_DM_ETH to all ls1021atwr_* defconfigs - Completely removed non-DM_ETH support from ls1021atwr - Changed "compatible" string from "fsl,tsec-mdio" to "fsl,etsec2-mdio" and from "fsl,tsec" to "fsl,etsec2" to match Linux
440 lines
11 KiB
Plaintext
440 lines
11 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Freescale ls1021a SOC common device tree source
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*
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* Copyright 2013-2015 Freescale Semiconductor, Inc.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "fsl,ls1021a";
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &lpuart0;
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serial1 = &lpuart1;
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serial2 = &lpuart2;
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serial3 = &lpuart3;
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serial4 = &lpuart4;
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serial5 = &lpuart5;
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sysclk = &sysclk;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@f00 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf00>;
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clocks = <&cluster1_clk>;
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};
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cpu@f01 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf01>;
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clocks = <&cluster1_clk>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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interrupt-parent = <&gic>;
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ranges;
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gic: interrupt-controller@1400000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x1401000 0x1000>,
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<0x1402000 0x1000>,
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<0x1404000 0x2000>,
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<0x1406000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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ifc: ifc@1530000 {
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compatible = "fsl,ifc", "simple-bus";
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reg = <0x1530000 0x10000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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};
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dcfg: dcfg@1ee0000 {
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compatible = "fsl,ls1021a-dcfg", "syscon";
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reg = <0x1ee0000 0x10000>;
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big-endian;
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};
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esdhc: esdhc@1560000 {
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compatible = "fsl,esdhc";
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reg = <0x1560000 0x10000>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <0>;
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voltage-ranges = <1800 1800 3300 3300>;
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sdhci,auto-cmd12;
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big-endian;
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bus-width = <4>;
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};
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scfg: scfg@1570000 {
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compatible = "fsl,ls1021a-scfg", "syscon";
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reg = <0x1570000 0x10000>;
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big-endian;
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};
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clockgen: clocking@1ee1000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x1ee1000 0x10000>;
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "sysclk";
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};
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cga_pll1: pll@800 {
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compatible = "fsl,qoriq-core-pll-2.0";
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#clock-cells = <1>;
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reg = <0x800 0x10>;
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clocks = <&sysclk>;
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clock-output-names = "cga-pll1", "cga-pll1-div2",
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"cga-pll1-div4";
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};
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platform_clk: pll@c00 {
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compatible = "fsl,qoriq-core-pll-2.0";
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#clock-cells = <1>;
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reg = <0xc00 0x10>;
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clocks = <&sysclk>;
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clock-output-names = "platform-clk", "platform-clk-div2";
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};
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cluster1_clk: clk0c0@0 {
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compatible = "fsl,qoriq-core-mux-2.0";
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#clock-cells = <0>;
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reg = <0x0 0x10>;
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clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
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clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
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clock-output-names = "cluster1-clk";
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};
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};
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dspi0: dspi@2100000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2100000 0x10000>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dspi";
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clocks = <&platform_clk 1>;
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num-cs = <6>;
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big-endian;
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status = "disabled";
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};
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dspi1: dspi@2110000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2110000 0x10000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dspi";
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clocks = <&platform_clk 1>;
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num-cs = <6>;
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big-endian;
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status = "disabled";
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};
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qspi: quadspi@1550000 {
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compatible = "fsl,vf610-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1550000 0x10000>,
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<0x40000000 0x4000000>;
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reg-names = "QuadSPI", "QuadSPI-memory";
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num-cs = <2>;
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big-endian;
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status = "disabled";
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};
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i2c0: i2c@2180000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2180000 0x10000>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&platform_clk 1>;
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status = "disabled";
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};
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i2c1: i2c@2190000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2190000 0x10000>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&platform_clk 1>;
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status = "disabled";
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};
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i2c2: i2c@21a0000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x21a0000 0x10000>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&platform_clk 1>;
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status = "disabled";
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};
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uart0: serial@21c0500 {
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compatible = "fsl,16550-FIFO64", "ns16550a";
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reg = <0x21c0500 0x100>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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fifo-size = <15>;
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status = "disabled";
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};
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uart1: serial@21c0600 {
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compatible = "fsl,16550-FIFO64", "ns16550a";
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reg = <0x21c0600 0x100>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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fifo-size = <15>;
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status = "disabled";
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};
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uart2: serial@21d0500 {
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compatible = "fsl,16550-FIFO64", "ns16550a";
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reg = <0x21d0500 0x100>;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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fifo-size = <15>;
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status = "disabled";
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};
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uart3: serial@21d0600 {
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compatible = "fsl,16550-FIFO64", "ns16550a";
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reg = <0x21d0600 0x100>;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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fifo-size = <15>;
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status = "disabled";
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};
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lpuart0: serial@2950000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x2950000 0x1000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sysclk>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart1: serial@2960000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x2960000 0x1000>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart2: serial@2970000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x2970000 0x1000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart3: serial@2980000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x2980000 0x1000>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart4: serial@2990000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x2990000 0x1000>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart5: serial@29a0000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x29a0000 0x1000>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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wdog0: watchdog@2ad0000 {
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compatible = "fsl,imx21-wdt";
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reg = <0x2ad0000 0x10000>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clock-names = "wdog-en";
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big-endian;
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};
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sai1: sai@2b50000 {
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compatible = "fsl,vf610-sai";
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reg = <0x2b50000 0x10000>;
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interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clock-names = "sai";
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dma-names = "tx", "rx";
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dmas = <&edma0 1 47>,
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<&edma0 1 46>;
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big-endian;
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status = "disabled";
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};
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sai2: sai@2b60000 {
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compatible = "fsl,vf610-sai";
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reg = <0x2b60000 0x10000>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clock-names = "sai";
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dma-names = "tx", "rx";
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dmas = <&edma0 1 45>,
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<&edma0 1 44>;
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big-endian;
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status = "disabled";
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};
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edma0: edma@2c00000 {
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#dma-cells = <2>;
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compatible = "fsl,vf610-edma";
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reg = <0x2c00000 0x10000>,
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<0x2c10000 0x10000>,
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<0x2c20000 0x10000>;
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interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma-tx", "edma-err";
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dma-channels = <32>;
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big-endian;
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clock-names = "dmamux0", "dmamux1";
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clocks = <&platform_clk 1>,
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<&platform_clk 1>;
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};
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enet0: ethernet@2d10000 {
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compatible = "fsl,etsec2";
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reg = <0x2d10000 0x1000>;
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status = "disabled";
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};
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enet1: ethernet@2d50000 {
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compatible = "fsl,etsec2";
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reg = <0x2d50000 0x1000>;
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status = "disabled";
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};
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enet2: ethernet@2d90000 {
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compatible = "fsl,etsec2";
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reg = <0x2d90000 0x1000>;
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status = "disabled";
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};
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mdio0: mdio@2d24000 {
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compatible = "fsl,etsec2-mdio";
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reg = <0x2d24000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mdio1: mdio@2d64000 {
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compatible = "fsl,etsec2-mdio";
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reg = <0x2d64000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usb@8600000 {
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compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
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reg = <0x8600000 0x1000>;
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interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
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dr_mode = "host";
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phy_type = "ulpi";
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};
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usb3@3100000 {
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compatible = "fsl,layerscape-dwc3";
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reg = <0x3100000 0x10000>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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dr_mode = "host";
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};
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pcie@3400000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x03400000 0x20000 /* dbi registers */
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0x01570000 0x10000 /* pf controls registers */
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0x24000000 0x20000>; /* configuration space */
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reg-names = "dbi", "ctrl", "config";
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big-endian;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */
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};
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pcie@3500000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x03500000 0x10000 /* dbi registers */
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0x01570000 0x10000 /* pf controls registers */
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0x34000000 0x20000>; /* configuration space */
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reg-names = "dbi", "ctrl", "config";
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big-endian;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <2>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */
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};
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sata: sata@3200000 {
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compatible = "fsl,ls1021a-ahci";
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reg = <0x3200000 0x10000 0x20220520 0x4>;
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reg-names = "sata-base", "ecc-addr";
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interrupts = <0 101 4>;
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status = "disabled";
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};
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};
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};
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