York Sun 2becdc6f9d powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram ... MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write through cache on E6500. L2 cache is enabled to to hold the data. This patch locks/unlocks L2 cache to ensure no data cast out from L2 cache. Signed-off-by: York Sun <yorksun@freescale.com> Reported-by: Jeffery Zhu <Jefferry.Zhu@freescale.com>		2015-09-01 20:42:54 -05:00
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cpu	powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram	2015-09-01 20:42:54 -05:00
dts	powerpc: gitignore: ignore PowerPC DTBs	2015-05-28 08:18:20 -04:00
include/asm	Correct License and Copyright information on few files	2015-08-12 20:47:46 -04:00
lib	ppc4xx: Remove sc3 board	2015-05-10 09:59:38 -04:00
config.mk	generic-board: move __HAVE_ARCH_GENERIC_BOARD to Kconfig	2015-03-28 09:03:08 -04:00
Kconfig	kbuild: create symbolic link only for ARM, AVR32, SPARC, PowerPC, x86	2015-07-27 15:02:00 -04:00
Makefile	Kbuild: introduce Makefile in arch/$ARCH/	2014-12-08 09:35:45 -05:00