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https://github.com/brain-hackers/u-boot-brain
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6d9b82d085
LS1088A is compliant with the Layerscape Chassis Generation 3 with eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4 SDRAM memory controller with ECC, Data path acceleration architecture 2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs), QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
45 lines
981 B
Makefile
45 lines
981 B
Makefile
#
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# Copyright 2014-2015, Freescale Semiconductor
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += cpu.o
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obj-y += lowlevel.o
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obj-y += soc.o
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obj-$(CONFIG_MP) += mp.o
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obj-$(CONFIG_OF_LIBFDT) += fdt.o
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obj-$(CONFIG_SPL) += spl.o
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obj-$(CONFIG_$(SPL_)FSL_LS_PPA) += ppa.o
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ifneq ($(CONFIG_FSL_LSCH3),)
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obj-y += fsl_lsch3_speed.o
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obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
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else
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ifneq ($(CONFIG_FSL_LSCH2),)
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obj-y += fsl_lsch2_speed.o
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obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o
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endif
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endif
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ifneq ($(CONFIG_ARCH_LS2080A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
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endif
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ifneq ($(CONFIG_ARCH_LS1043A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
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obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o
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endif
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ifneq ($(CONFIG_ARCH_LS1012A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
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endif
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ifneq ($(CONFIG_ARCH_LS1046A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
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endif
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ifneq ($(CONFIG_ARCH_LS1088A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
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endif
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