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https://github.com/brain-hackers/u-boot-brain
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63b2316c5c
CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com> |
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| .. | ||
| clock.c | ||
| cpu.c | ||
| fdt.c | ||
| fsl_epu.c | ||
| fsl_epu.h | ||
| fsl_ls1_serdes.c | ||
| fsl_ls1_serdes.h | ||
| Kconfig | ||
| ls102xa_psci.c | ||
| ls102xa_sata.c | ||
| ls102xa_serdes.c | ||
| Makefile | ||
| psci.S | ||
| soc.c | ||
| spl.c | ||
| timer.c | ||