Sebastian Reichel 717bf50f4b board: ge: bx50v3: cleanup phy config ... The current PHY rework does the following things: 1. Configure 125MHz clock 2. Setup the TX clock delay (RX is enabled by default), 3. Setup reserved bits to avoid voltage peak The clock delays are nowadays already configured by the PHY driver (in ar803x_delay_config). The code for that can simply be dropped. The clock speed can also be configured by the PHY driver by adding the device tree property "qca,clk-out-frequency". What is left is setting up the undocumented reserved bits to avoid the voltage peak problem. I slightly improved its documentation while updating the board's PHY rework code. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>		2020-12-26 14:56:09 +01:00
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bx50v3.c	board: ge: bx50v3: cleanup phy config	2020-12-26 14:56:09 +01:00
bx50v3.cfg	doc: update reference to README.imximage	2020-04-16 23:06:54 -04:00
Kconfig	board: ge: common: add config option for RTC and VPD feature	2020-11-01 15:58:47 +01:00
MAINTAINERS	board: ge: bx50v3: Update MAINTAINERS	2020-11-04 19:47:01 +01:00
Makefile	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00