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board: ge: bx50v3: cleanup phy config

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The current PHY rework does the following things:

1. Configure 125MHz clock
2. Setup the TX clock delay (RX is enabled by default),
3. Setup reserved bits to avoid voltage peak

The clock delays are nowadays already configured by the
PHY driver (in ar803x_delay_config). The code for that
can simply be dropped. The clock speed can also be
configured by the PHY driver by adding the device tree
property "qca,clk-out-frequency".

What is left is setting up the undocumented reserved bits
to avoid the voltage peak problem. I slightly improved its
documentation while updating the board's PHY rework code.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
This commit is contained in:
Sebastian Reichel 2020-12-15 00:41:57 +01:00 committed by Stefano Babic
parent c44d374bef
commit 717bf50f4b
2 changed files with 23 additions and 23 deletions
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11
arch/arm/dts/imx6q-ba16.dtsi
View File

@ -174,6 +174,17 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
status = "okay";
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@4 {
reg = <4>;
qca,clk-out-frequency = <125000000>;
};
};
};
&hdmi {

35
board/ge/bx50v3/bx50v3.c
View File

@ -47,6 +47,10 @@ DECLARE_GLOBAL_DATA_PTR;
#define VPD_PRODUCT_B650 2
#define VPD_PRODUCT_B450 3
#define AR8033_DBG_REG_ADDR 0x1d
#define AR8033_DBG_REG_DATA 0x1e
#define AR8033_SERDES_REG 0x5
static int productid; /* Default to generic. */
static struct vpd_cache vpd;
@ -61,31 +65,16 @@ int dram_init(void)
return 0;
}
static int mx6_rgmii_rework(struct phy_device *phydev)
{
/* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
/* set device address 0x7 */
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
/* offset 0x8016: CLK_25M Clock Select */
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
/* enable register write, no post increment, address 0x7 */
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
/* set to 125 MHz from local PLL source */
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
/* rgmii tx clock delay enable */
/* set debug port address: SerDes Test and System Mode Control */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
/* enable rgmii tx clock delay */
/* set the reserved bits to avoid board specific voltage peak issue*/
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
mx6_rgmii_rework(phydev);
/*
* Set reserved bits to avoid board specific voltage peak issue. The
* value is a magic number provided directly by Qualcomm. Note, that
* PHY driver will take control of BIT(8) in this register to control
* TX clock delay, so we do not initialize that bit here.
*/
phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_ADDR, AR8033_SERDES_REG);
phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_DATA, 0x3c47);
if (phydev->drv->config)
phydev->drv->config(phydev);